862 lines
23 KiB
C
862 lines
23 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2000 Silicon Integrated System Corporation
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* Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Contains the chipset specific flash enables.
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*/
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#define _LARGEFILE64_SOURCE
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#include <stdio.h>
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#include <pci/pci.h>
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#include <stdlib.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <sys/mman.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include "flash.h"
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/**
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* flashrom defaults to LPC flash devices. If a known SPI controller is found
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* and the SPI strappings are set, this will be overwritten by the probing code.
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*
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* Eventually, this will become an array when multiple flash support works.
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*/
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flashbus_t flashbus = BUS_TYPE_LPC;
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void *spibar = NULL;
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static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
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{
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uint8_t tmp;
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/*
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* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
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* 0xFFFE0000-0xFFFFFFFF ROM select enable.
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*/
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tmp = pci_read_byte(dev, 0x47);
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tmp |= 0x46;
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pci_write_byte(dev, 0x47, tmp);
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return 0;
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}
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static int enable_flash_sis630(struct pci_dev *dev, const char *name)
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{
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uint8_t b;
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/* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
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b = pci_read_byte(dev, 0x40);
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pci_write_byte(dev, 0x40, b | 0xb);
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/* Flash write enable on SiS 540/630. */
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b = pci_read_byte(dev, 0x45);
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pci_write_byte(dev, 0x45, b | 0x40);
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/* The same thing on SiS 950 Super I/O side... */
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/* First probe for Super I/O on config port 0x2e. */
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OUTB(0x87, 0x2e);
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OUTB(0x01, 0x2e);
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OUTB(0x55, 0x2e);
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OUTB(0x55, 0x2e);
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if (INB(0x2f) != 0x87) {
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/* If that failed, try config port 0x4e. */
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OUTB(0x87, 0x4e);
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OUTB(0x01, 0x4e);
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OUTB(0x55, 0x4e);
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OUTB(0xaa, 0x4e);
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if (INB(0x4f) != 0x87) {
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printf("Can not access SiS 950\n");
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return -1;
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}
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OUTB(0x24, 0x4e);
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b = INB(0x4f) | 0xfc;
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OUTB(0x24, 0x4e);
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OUTB(b, 0x4f);
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OUTB(0x02, 0x4e);
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OUTB(0x02, 0x4f);
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}
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OUTB(0x24, 0x2e);
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printf("2f is %#x\n", INB(0x2f));
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b = INB(0x2f) | 0xfc;
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OUTB(0x24, 0x2e);
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OUTB(b, 0x2f);
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OUTB(0x02, 0x2e);
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OUTB(0x02, 0x2f);
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return 0;
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}
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/* Datasheet:
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* - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
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* - URL: http://www.intel.com/design/intarch/datashts/290562.htm
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* - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
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* - Order Number: 290562-001
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*/
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static int enable_flash_piix4(struct pci_dev *dev, const char *name)
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{
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uint16_t old, new;
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uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
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old = pci_read_word(dev, xbcs);
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/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
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* FFF00000-FFF7FFFF are forwarded to ISA).
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* Note: This bit is reserved on PIIX/PIIX3/MPIIX.
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* Set bit 7: Extended BIOS Enable (PCI master accesses to
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* FFF80000-FFFDFFFF are forwarded to ISA).
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* Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
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* the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
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* of 1 Mbyte, or the aliases at the top of 4 Gbyte
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* (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
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* Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
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* Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
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*/
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if (dev->device_id == 0x122e || dev->device_id == 0x7000
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|| dev->device_id == 0x1234)
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new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
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else
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new = old | 0x02c4;
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if (new == old)
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return 0;
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pci_write_word(dev, xbcs, new);
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if (pci_read_word(dev, xbcs) != new) {
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printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
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return -1;
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}
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return 0;
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}
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/*
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* See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
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* http://download.intel.com/design/chipsets/datashts/30701303.pdf
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*/
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static int enable_flash_ich(struct pci_dev *dev, const char *name,
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int bios_cntl)
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{
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uint8_t old, new;
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/*
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* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
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* just treating it as 8 bit wide seems to work fine in practice.
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*/
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old = pci_read_byte(dev, bios_cntl);
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printf_debug("\nBIOS Lock Enable: %sabled, ",
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(old & (1 << 1)) ? "en" : "dis");
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printf_debug("BIOS Write Enable: %sabled, ",
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(old & (1 << 0)) ? "en" : "dis");
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printf_debug("BIOS_CNTL is 0x%x\n", old);
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new = old | 1;
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if (new == old)
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return 0;
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pci_write_byte(dev, bios_cntl, new);
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if (pci_read_byte(dev, bios_cntl) != new) {
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printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
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return -1;
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}
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return 0;
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}
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static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
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{
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return enable_flash_ich(dev, name, 0x4e);
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}
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static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
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{
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return enable_flash_ich(dev, name, 0xdc);
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}
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#define ICH_STRAP_RSVD 0x00
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#define ICH_STRAP_SPI 0x01
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#define ICH_STRAP_PCI 0x02
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#define ICH_STRAP_LPC 0x03
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static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
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{
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uint32_t mmio_base;
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mmio_base = (pci_read_long(dev, 0xbc)) << 8;
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printf_debug("MMIO base at = 0x%x\n", mmio_base);
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spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
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fd_mem, mmio_base);
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if (spibar == MAP_FAILED) {
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perror("Can't mmap memory using " MEM_DEV);
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exit(1);
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}
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printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
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*(uint16_t *) (spibar + 0x6c));
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flashbus = BUS_TYPE_VIA_SPI;
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return 0;
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}
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static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
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int ich_generation)
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{
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int ret, i;
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uint8_t old, new, bbs, buc;
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uint16_t spibar_offset;
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uint32_t tmp, gcs;
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void *rcrb;
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static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
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/* Enable Flash Writes */
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ret = enable_flash_ich_dc(dev, name);
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/* Get physical address of Root Complex Register Block */
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tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
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printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
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/* Map RCBA to virtual memory */
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rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem,
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(off_t) tmp);
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if (rcrb == MAP_FAILED) {
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perror("Can't mmap memory using " MEM_DEV);
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exit(1);
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}
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gcs = *(volatile uint32_t *)(rcrb + 0x3410);
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printf_debug("GCS = 0x%x: ", gcs);
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printf_debug("BIOS Interface Lock-Down: %sabled, ",
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(gcs & 0x1) ? "en" : "dis");
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bbs = (gcs >> 10) & 0x3;
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printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
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buc = *(volatile uint8_t *)(rcrb + 0x3414);
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printf_debug("Top Swap : %s\n",
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(buc & 1) ? "enabled (A16 inverted)" : "not enabled");
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/* It seems the ICH7 does not support SPI and LPC chips at the same
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* time. At least not with our current code. So we prevent searching
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* on ICH7 when the southbridge is strapped to LPC
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*/
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if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
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/* No further SPI initialization required */
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return ret;
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}
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switch (ich_generation) {
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case 7:
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flashbus = BUS_TYPE_ICH7_SPI;
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spibar_offset = 0x3020;
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break;
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case 8:
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flashbus = BUS_TYPE_ICH9_SPI;
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spibar_offset = 0x3020;
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break;
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case 9:
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case 10:
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default: /* Future version might behave the same */
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flashbus = BUS_TYPE_ICH9_SPI;
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spibar_offset = 0x3800;
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break;
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}
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/* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
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printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
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/* Assign Virtual Address */
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spibar = rcrb + spibar_offset;
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switch (flashbus) {
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case BUS_TYPE_ICH7_SPI:
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printf_debug("0x00: 0x%04x (SPIS)\n",
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*(uint16_t *) (spibar + 0));
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printf_debug("0x02: 0x%04x (SPIC)\n",
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*(uint16_t *) (spibar + 2));
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printf_debug("0x04: 0x%08x (SPIA)\n",
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*(uint32_t *) (spibar + 4));
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for (i = 0; i < 8; i++) {
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int offs;
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offs = 8 + (i * 8);
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printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
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*(uint32_t *) (spibar + offs), i);
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printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
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*(uint32_t *) (spibar + offs + 4), i);
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}
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printf_debug("0x50: 0x%08x (BBAR)\n",
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*(uint32_t *) (spibar + 0x50));
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printf_debug("0x54: 0x%04x (PREOP)\n",
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*(uint16_t *) (spibar + 0x54));
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printf_debug("0x56: 0x%04x (OPTYPE)\n",
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*(uint16_t *) (spibar + 0x56));
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printf_debug("0x58: 0x%08x (OPMENU)\n",
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*(uint32_t *) (spibar + 0x58));
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printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
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*(uint32_t *) (spibar + 0x5c));
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for (i = 0; i < 4; i++) {
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int offs;
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offs = 0x60 + (i * 4);
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printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
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*(uint32_t *) (spibar + offs), i);
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}
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printf_debug("\n");
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if ((*(uint16_t *) spibar) & (1 << 15)) {
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printf("WARNING: SPI Configuration Lockdown activated.\n");
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}
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break;
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case BUS_TYPE_ICH9_SPI:
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/* TODO: Add dumping function for ICH8/ICH9, or drop the
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* whole SPIBAR dumping from chipset_enable.c - There's
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* inteltool for this task already.
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*/
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break;
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default:
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/* Nothing */
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break;
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}
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old = pci_read_byte(dev, 0xdc);
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printf_debug("SPI Read Configuration: ");
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new = (old >> 2) & 0x3;
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switch (new) {
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case 0:
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case 1:
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case 2:
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printf_debug("prefetching %sabled, caching %sabled, ",
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(new & 0x2) ? "en" : "dis",
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(new & 0x1) ? "dis" : "en");
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break;
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default:
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printf_debug("invalid prefetching/caching settings, ");
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break;
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}
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return ret;
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}
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static int enable_flash_ich7(struct pci_dev *dev, const char *name)
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{
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return enable_flash_ich_dc_spi(dev, name, 7);
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}
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static int enable_flash_ich8(struct pci_dev *dev, const char *name)
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{
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return enable_flash_ich_dc_spi(dev, name, 8);
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}
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static int enable_flash_ich9(struct pci_dev *dev, const char *name)
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{
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return enable_flash_ich_dc_spi(dev, name, 9);
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}
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static int enable_flash_ich10(struct pci_dev *dev, const char *name)
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{
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return enable_flash_ich_dc_spi(dev, name, 10);
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}
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static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
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{
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uint8_t val;
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/* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
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pci_write_byte(dev, 0x41, 0x7f);
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/* ROM write enable */
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val = pci_read_byte(dev, 0x40);
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val |= 0x10;
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pci_write_byte(dev, 0x40, val);
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if (pci_read_byte(dev, 0x40) != val) {
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printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
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name);
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return -1;
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}
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return 0;
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}
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static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
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{
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uint8_t reg8;
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#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
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#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
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#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
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#define ROM_WRITE_ENABLE (1 << 1)
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#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
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#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
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/* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
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* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
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* Make the configured ROM areas writable.
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*/
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reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
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reg8 |= LOWER_ROM_ADDRESS_RANGE;
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reg8 |= UPPER_ROM_ADDRESS_RANGE;
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reg8 |= ROM_WRITE_ENABLE;
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pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
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/* Set positive decode on ROM. */
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reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
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reg8 |= BIOS_ROM_POSITIVE_DECODE;
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pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
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return 0;
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}
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/**
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* Geode systems write protect the BIOS via RCONFs (cache settings similar
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* to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
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* writing to MSRs, however requires instructions rdmsr/wrmsr, which are
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* ring0 privileged instructions so only the kernel can do the read/write.
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* This function, therefore, requires that the msr kernel module be loaded
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* to access these instructions from user space using device /dev/cpu/0/msr.
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*
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* This hard-coded location could have potential problems on SMP machines
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* since it assumes cpu0, but it is safe on the Geode which is not SMP.
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*
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* Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
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* To enable write to NOR Boot flash for the benefit of systems that have such
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* a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
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*
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* This is probably not portable beyond Linux.
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*/
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static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
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{
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#define MSR_RCONF_DEFAULT 0x1808
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#define MSR_NORF_CTL 0x51400018
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int fd_msr;
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unsigned char buf[8];
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fd_msr = open("/dev/cpu/0/msr", O_RDWR);
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if (!fd_msr) {
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perror("open msr");
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return -1;
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}
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if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
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perror("lseek64");
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printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
|
|
close(fd_msr);
|
|
return -1;
|
|
}
|
|
|
|
if (read(fd_msr, buf, 8) != 8) {
|
|
perror("read msr");
|
|
close(fd_msr);
|
|
return -1;
|
|
}
|
|
|
|
if (buf[7] != 0x22) {
|
|
buf[7] &= 0xfb;
|
|
if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT,
|
|
SEEK_SET) == -1) {
|
|
perror("lseek64");
|
|
close(fd_msr);
|
|
return -1;
|
|
}
|
|
|
|
if (write(fd_msr, buf, 8) < 0) {
|
|
perror("msr write");
|
|
close(fd_msr);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
|
|
perror("lseek64");
|
|
close(fd_msr);
|
|
return -1;
|
|
}
|
|
|
|
if (read(fd_msr, buf, 8) != 8) {
|
|
perror("read msr");
|
|
close(fd_msr);
|
|
return -1;
|
|
}
|
|
|
|
/* Raise WE_CS3 bit. */
|
|
buf[0] |= 0x08;
|
|
|
|
if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
|
|
perror("lseek64");
|
|
close(fd_msr);
|
|
return -1;
|
|
}
|
|
if (write(fd_msr, buf, 8) < 0) {
|
|
perror("msr write");
|
|
close(fd_msr);
|
|
return -1;
|
|
}
|
|
|
|
close(fd_msr);
|
|
|
|
#undef MSR_RCONF_DEFAULT
|
|
#undef MSR_NORF_CTL
|
|
return 0;
|
|
}
|
|
|
|
static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
|
|
{
|
|
uint8_t new;
|
|
|
|
pci_write_byte(dev, 0x52, 0xee);
|
|
|
|
new = pci_read_byte(dev, 0x52);
|
|
|
|
if (new != 0xee) {
|
|
printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
|
|
{
|
|
uint8_t new, newer;
|
|
|
|
new = pci_read_byte(dev, 0x45);
|
|
|
|
new &= (~0x20); /* Clear bit 5. */
|
|
new |= 0x4; /* Set bit 2. */
|
|
|
|
pci_write_byte(dev, 0x45, new);
|
|
|
|
newer = pci_read_byte(dev, 0x45);
|
|
if (newer != new) {
|
|
printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
|
|
printf("Stuck at 0x%x\n", newer);
|
|
return -1;
|
|
}
|
|
|
|
/* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
|
|
new = pci_read_byte(dev, 0x40);
|
|
new &= 0xFB;
|
|
new |= 0x3;
|
|
pci_write_byte(dev, 0x40, new);
|
|
newer = pci_read_byte(dev, 0x40);
|
|
if (newer != new) {
|
|
printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
|
|
printf("Stuck at 0x%x\n", newer);
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
|
|
static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
|
|
{
|
|
uint8_t old, new;
|
|
|
|
/* Enable decoding at 0xffb00000 to 0xffffffff. */
|
|
old = pci_read_byte(dev, 0x43);
|
|
new = old | 0xC0;
|
|
if (new != old) {
|
|
pci_write_byte(dev, 0x43, new);
|
|
if (pci_read_byte(dev, 0x43) != new) {
|
|
printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
|
|
}
|
|
}
|
|
|
|
/* Enable 'ROM write' bit. */
|
|
old = pci_read_byte(dev, 0x40);
|
|
new = old | 0x01;
|
|
if (new == old)
|
|
return 0;
|
|
pci_write_byte(dev, 0x40, new);
|
|
|
|
if (pci_read_byte(dev, 0x40) != new) {
|
|
printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int enable_flash_sb600(struct pci_dev *dev, const char *name)
|
|
{
|
|
uint32_t old, new;
|
|
uint8_t reg;
|
|
|
|
/* Clear ROM Protect 0-3 */
|
|
for (reg = 0x50; reg < 0x60; reg += 4) {
|
|
old = pci_read_long(dev, reg);
|
|
new = old & 0xFFFFFFFC;
|
|
if (new != old) {
|
|
pci_write_byte(dev, reg, new);
|
|
if (pci_read_long(dev, reg) != new) {
|
|
printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x50, new, name);
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int enable_flash_ck804(struct pci_dev *dev, const char *name)
|
|
{
|
|
uint8_t old, new;
|
|
|
|
old = pci_read_byte(dev, 0x88);
|
|
new = old | 0xc0;
|
|
if (new != old) {
|
|
pci_write_byte(dev, 0x88, new);
|
|
if (pci_read_byte(dev, 0x88) != new) {
|
|
printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
|
|
}
|
|
}
|
|
|
|
old = pci_read_byte(dev, 0x6d);
|
|
new = old | 0x01;
|
|
if (new == old)
|
|
return 0;
|
|
pci_write_byte(dev, 0x6d, new);
|
|
|
|
if (pci_read_byte(dev, 0x6d) != new) {
|
|
printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
|
|
static int enable_flash_sb400(struct pci_dev *dev, const char *name)
|
|
{
|
|
uint8_t tmp;
|
|
struct pci_filter f;
|
|
struct pci_dev *smbusdev;
|
|
|
|
/* Look for the SMBus device. */
|
|
pci_filter_init((struct pci_access *)0, &f);
|
|
f.vendor = 0x1002;
|
|
f.device = 0x4372;
|
|
|
|
for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
|
|
if (pci_filter_match(&f, smbusdev))
|
|
break;
|
|
}
|
|
|
|
if (!smbusdev) {
|
|
fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
|
|
exit(1);
|
|
}
|
|
|
|
/* Enable some SMBus stuff. */
|
|
tmp = pci_read_byte(smbusdev, 0x79);
|
|
tmp |= 0x01;
|
|
pci_write_byte(smbusdev, 0x79, tmp);
|
|
|
|
/* Change southbridge. */
|
|
tmp = pci_read_byte(dev, 0x48);
|
|
tmp |= 0x21;
|
|
pci_write_byte(dev, 0x48, tmp);
|
|
|
|
/* Now become a bit silly. */
|
|
tmp = INB(0xc6f);
|
|
OUTB(tmp, 0xeb);
|
|
OUTB(tmp, 0xeb);
|
|
tmp |= 0x40;
|
|
OUTB(tmp, 0xc6f);
|
|
OUTB(tmp, 0xeb);
|
|
OUTB(tmp, 0xeb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
|
|
{
|
|
uint8_t old, new, byte;
|
|
uint16_t word;
|
|
|
|
/* Set the 0-16 MB enable bits. */
|
|
byte = pci_read_byte(dev, 0x88);
|
|
byte |= 0xff; /* 256K */
|
|
pci_write_byte(dev, 0x88, byte);
|
|
byte = pci_read_byte(dev, 0x8c);
|
|
byte |= 0xff; /* 1M */
|
|
pci_write_byte(dev, 0x8c, byte);
|
|
word = pci_read_word(dev, 0x90);
|
|
word |= 0x7fff; /* 16M */
|
|
pci_write_word(dev, 0x90, word);
|
|
|
|
old = pci_read_byte(dev, 0x6d);
|
|
new = old | 0x01;
|
|
if (new == old)
|
|
return 0;
|
|
pci_write_byte(dev, 0x6d, new);
|
|
|
|
if (pci_read_byte(dev, 0x6d) != new) {
|
|
printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
|
|
{
|
|
uint8_t byte;
|
|
|
|
/* Set the 4MB enable bit. */
|
|
byte = pci_read_byte(dev, 0x41);
|
|
byte |= 0x0e;
|
|
pci_write_byte(dev, 0x41, byte);
|
|
|
|
byte = pci_read_byte(dev, 0x43);
|
|
byte |= (1 << 4);
|
|
pci_write_byte(dev, 0x43, byte);
|
|
|
|
return 0;
|
|
}
|
|
|
|
typedef struct penable {
|
|
uint16_t vendor, device;
|
|
const char *name;
|
|
int (*doit) (struct pci_dev *dev, const char *name);
|
|
} FLASH_ENABLE;
|
|
|
|
static const FLASH_ENABLE enables[] = {
|
|
{0x1039, 0x0630, "SiS630", enable_flash_sis630},
|
|
{0x8086, 0x122e, "Intel PIIX", enable_flash_piix4},
|
|
{0x8086, 0x1234, "Intel MPIIX", enable_flash_piix4},
|
|
{0x8086, 0x7000, "Intel PIIX3", enable_flash_piix4},
|
|
{0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
|
|
{0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
|
|
{0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},
|
|
{0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e},
|
|
{0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e},
|
|
{0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e},
|
|
{0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e},
|
|
{0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e},
|
|
{0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e},
|
|
{0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e},
|
|
{0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e},
|
|
{0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e},
|
|
{0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
|
|
{0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
|
|
{0x8086, 0x5031, "Intel EP80579", enable_flash_ich_dc},
|
|
{0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7},
|
|
{0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7},
|
|
{0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7},
|
|
{0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich7},
|
|
{0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich8},
|
|
{0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich8},
|
|
{0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich8},
|
|
{0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich8},
|
|
{0x8086, 0x2815, "Intel ICH8M", enable_flash_ich8},
|
|
{0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich9},
|
|
{0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich9},
|
|
{0x8086, 0x2916, "Intel ICH9R", enable_flash_ich9},
|
|
{0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich9},
|
|
{0x8086, 0x2918, "Intel ICH9", enable_flash_ich9},
|
|
{0x8086, 0x2919, "Intel ICH9M", enable_flash_ich9},
|
|
{0x8086, 0x3a14, "Intel ICH10DO", enable_flash_ich10},
|
|
{0x8086, 0x3a16, "Intel ICH10R", enable_flash_ich10},
|
|
{0x8086, 0x3a18, "Intel ICH10", enable_flash_ich10},
|
|
{0x8086, 0x3a1a, "Intel ICH10D", enable_flash_ich10},
|
|
{0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x},
|
|
{0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x},
|
|
{0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
|
|
{0x1106, 0x3372, "VIA VT8237S", enable_flash_vt8237s_spi},
|
|
{0x1106, 0x8324, "VIA CX700", enable_flash_vt823x},
|
|
{0x1106, 0x0586, "VIA VT82C586A/B", enable_flash_amd8111},
|
|
{0x1106, 0x0686, "VIA VT82C686A/B", enable_flash_amd8111},
|
|
{0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530},
|
|
{0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100},
|
|
{0x1039, 0x0008, "SiS5595", enable_flash_sis5595},
|
|
{0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536},
|
|
{0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
|
|
{0x1002, 0x438D, "ATI(AMD) SB600", enable_flash_sb600},
|
|
{0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
|
|
{0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
|
|
{0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
|
|
/* Slave, should not be here, to fix known bug for A01. */
|
|
{0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804},
|
|
{0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804},
|
|
{0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804},
|
|
{0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804},
|
|
{0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804},
|
|
{0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/
|
|
{0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
|
{0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
|
{0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
|
{0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
|
{0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
|
{0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
|
{0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
|
|
{0x10de, 0x0548, "NVIDIA MCP67", enable_flash_mcp55},
|
|
{0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
|
|
{0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
|
|
};
|
|
|
|
void print_supported_chipsets(void)
|
|
{
|
|
int i;
|
|
|
|
printf("\nSupported chipsets:\n\n");
|
|
|
|
for (i = 0; i < ARRAY_SIZE(enables); i++)
|
|
printf("%s (%04x:%04x)\n", enables[i].name,
|
|
enables[i].vendor, enables[i].device);
|
|
}
|
|
|
|
int chipset_flash_enable(void)
|
|
{
|
|
struct pci_dev *dev = 0;
|
|
int ret = -2; /* Nothing! */
|
|
int i;
|
|
|
|
/* Now let's try to find the chipset we have... */
|
|
for (i = 0; i < ARRAY_SIZE(enables); i++) {
|
|
dev = pci_dev_find(enables[i].vendor, enables[i].device);
|
|
if (dev)
|
|
break;
|
|
}
|
|
|
|
if (dev) {
|
|
printf("Found chipset \"%s\", enabling flash write... ",
|
|
enables[i].name);
|
|
|
|
ret = enables[i].doit(dev, enables[i].name);
|
|
if (ret)
|
|
printf("FAILED!\n");
|
|
else
|
|
printf("OK.\n");
|
|
}
|
|
|
|
return ret;
|
|
}
|