6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
80 lines
2 KiB
C
80 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <northbridge/intel/ironlake/ironlake.h>
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#include "pch.h"
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/* This sets up magic Chipset Initialization Registers */
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void pch_setup_cir(int chipset_type)
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{
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printk(BIOS_DEBUG, "Setting up Chipset Initialization Registers (CIR)\n");
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uint16_t lpc_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID);
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struct cpuinfo_x86 c;
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uint32_t cir22;
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pci_or_config8(PCH_LPC_DEV, GEN_PMCON_3, 0xfb);
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RCBA32_OR(GCS, 0x40); /* FERR# MUX enable */
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RCBA8(0x3430) |= 0xfc;
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RCBA32(CIR7) = 0xf;
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RCBA32(CIR9) = 0;
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switch (lpc_id) {
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case 0x3b01:
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case 0x3b03:
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case 0x3b05:
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case 0x3b07:
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case 0x3b09:
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case 0x3b0b:
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case 0x3b0d:
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case 0x3b0f:
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RCBA32_AND_OR(CIR6, 0xff1fff7f, 0x600000);
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break;
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}
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RCBA32_OR(0x3310, 0x31);
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/* Intel 5 Series Chipset and Intel 3400 Series Chipset
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External Design Specification (EDS) 13.8.1.1 */
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if (chipset_type == IRONLAKE_DESKTOP)
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pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3);
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pci_write_config8(PCH_LPC_DEV, CIR4, 0x45);
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RCBA32(CIR8) = 0x4000000;
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pci_write_config32(PCH_LPC_DEV, PMIR, 0xc0000300);
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RCBA32(0x3318) = 0x1020000; /* undocumented */
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get_fms(&c, cpuid_eax(1));
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if (c.x86_model == 0x1e) {
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/* Lynnfield/Clarksfield */
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RCBA32(CIR13) = 0xfffff;
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RCBA32(CIR14) = 0x61080;
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RCBA32(CIR16) = 0x7f8f9f80;
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RCBA32(CIR18) = 0x3900;
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RCBA32(CIR19) = 0x20002;
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RCBA32(CIR20) = 0x44b00;
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RCBA32(CIR21) = 0x02000;
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cir22 = 0x20000;
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} else if (c.x86_model == 0x1f || c.x86_model == 0x25) {
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/* Auburndale/Havendale + Arrandale/Clarkdale */
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RCBA32(CIR10) = 0xfff80;
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RCBA32(CIR15) = 0x7f8f9fff;
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RCBA32(CIR17) = 0x2900;
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RCBA32(CIR19) = 0x10001;
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RCBA32(CIR20) = 0x1004b;
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RCBA32(CIR21) = 0x8;
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cir22 = 0x10000;
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} else {
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die("unsupported CPU model: %x!\n", c.x86_model);
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}
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/* EDS, 10.1.77: Program this register after all registers in the
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3330-33D3 range and D31:F0:A9h are already programmed */
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RCBA32(CIR22) = cir22;
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}
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