Ronak Kanabar b6a523927d soc/intel/jasperlake: Remove DDI A lane programming ... For newer Intel graphics (>=11), the DDI port max lanes default to 4. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A (for DDI port A) register programming. Hence removing this code. BUG=b:150788968 BRANCH=None TEST=checked jslrvp compilation and boot. Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40038 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-04-06 11:06:53 +00:00
..
acpi
bootblock
include/soc
romstage	soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC	2020-04-01 16:39:28 +00:00
acpi.c
chip.c	Trim .acpi_fill_ssdt_generator and .acpi_inject_dsdt_generator	2020-04-02 20:30:22 +00:00
chip.h
cpu.c
elog.c
espi.c
finalize.c
fsp_params.c
gpio.c
graphics.c	soc/intel/jasperlake: Remove DDI A lane programming	2020-04-06 11:06:53 +00:00
gspi.c
i2c.c
Kconfig	fsp2_0: Gather Kconfig declarations	2020-04-05 23:26:24 +00:00
lockdown.c
Makefile.inc	soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC	2020-04-01 16:39:28 +00:00
meminit.c
p2sb.c
pmc.c
pmutil.c
reset.c
sd.c
smihandler.c
smmrelocate.c
spi.c
systemagent.c
uart.c