ef3f7e38ea
The AT45 series SPI chips are DataFlash EEPROMs which means they have odd (non-power-of-two) sector sizes, but some of the DataFlash chips can be configured or ordered with power-of-two sector sizes. Add probe support for the following Atmel SPI chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 AT45CS1282 AT45DB011D AT45DB021D AT45DB041D AT45DB081D AT45DB161D AT45DB321C AT45DB321D AT45DB642D Add an explanation why the following chips can't be probed: AT45BR3214B AT45D011 AT45D021A AT45D041A AT45D081A AT45D161 AT45DB011 AT45DB011B AT45DB021A AT45DB021B AT45DB041A AT45DB081A AT45DB161 AT45DB161B AT45DB321 AT45DB321B AT45DB642 Add the ID, but no probing function for this chip: AT25F512A Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
/*
|
|
* This file is part of the flashrom project.
|
|
*
|
|
* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
*/
|
|
|
|
#ifndef __SPI_H__
|
|
#define __SPI_H__ 1
|
|
|
|
/*
|
|
* Contains the generic SPI headers
|
|
*/
|
|
|
|
/* Read Electronic ID */
|
|
#define JEDEC_RDID 0x9f
|
|
#define JEDEC_RDID_OUTSIZE 0x01
|
|
#define JEDEC_RDID_INSIZE 0x03
|
|
|
|
/* Read Electronic Signature */
|
|
#define JEDEC_RES 0xab
|
|
#define JEDEC_RES_OUTSIZE 0x04
|
|
#define JEDEC_RES_INSIZE 0x01
|
|
|
|
/* Write Enable */
|
|
#define JEDEC_WREN 0x06
|
|
#define JEDEC_WREN_OUTSIZE 0x01
|
|
#define JEDEC_WREN_INSIZE 0x00
|
|
|
|
/* Write Disable */
|
|
#define JEDEC_WRDI 0x04
|
|
#define JEDEC_WRDI_OUTSIZE 0x01
|
|
#define JEDEC_WRDI_INSIZE 0x00
|
|
|
|
/* Chip Erase 0x60 is supported by Macronix/SST chips. */
|
|
#define JEDEC_CE_60 0x60
|
|
#define JEDEC_CE_60_OUTSIZE 0x01
|
|
#define JEDEC_CE_60_INSIZE 0x00
|
|
|
|
/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
|
|
#define JEDEC_CE_C7 0xc7
|
|
#define JEDEC_CE_C7_OUTSIZE 0x01
|
|
#define JEDEC_CE_C7_INSIZE 0x00
|
|
|
|
/* Block Erase 0x52 is supported by SST and old Atmel chips. */
|
|
#define JEDEC_BE_52 0x52
|
|
#define JEDEC_BE_52_OUTSIZE 0x04
|
|
#define JEDEC_BE_52_INSIZE 0x00
|
|
|
|
/* Block Erase 0xd8 is supported by EON/Macronix chips. */
|
|
#define JEDEC_BE_D8 0xd8
|
|
#define JEDEC_BE_D8_OUTSIZE 0x04
|
|
#define JEDEC_BE_D8_INSIZE 0x00
|
|
|
|
/* Sector Erase 0x20 is supported by Macronix/SST chips. */
|
|
#define JEDEC_SE 0x20
|
|
#define JEDEC_SE_OUTSIZE 0x04
|
|
#define JEDEC_SE_INSIZE 0x00
|
|
|
|
/* Read Status Register */
|
|
#define JEDEC_RDSR 0x05
|
|
#define JEDEC_RDSR_OUTSIZE 0x01
|
|
#define JEDEC_RDSR_INSIZE 0x01
|
|
#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
|
|
|
|
/* Write Status Register */
|
|
#define JEDEC_WRSR 0x01
|
|
#define JEDEC_WRSR_OUTSIZE 0x02
|
|
#define JEDEC_WRSR_INSIZE 0x00
|
|
|
|
/* Read the memory */
|
|
#define JEDEC_READ 0x03
|
|
#define JEDEC_READ_OUTSIZE 0x04
|
|
/* JEDEC_READ_INSIZE : any length */
|
|
|
|
/* Write memory byte */
|
|
#define JEDEC_BYTE_PROGRAM 0x02
|
|
#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
|
|
#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
|
|
|
|
#endif /* !__SPI_H__ */
|