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Hung-Te Lin b763b37411 mb/google/kukui: Extend FMAP to 8MB layout
The SPI flash component requirement for Kukui family is 8M so we should
update FMAP for that:

- Add more comments for alignment and size recommendation.
- Enlarge RO to 4M, and RW_SECTION_{A,B} both ~1.5M.
- BOOTBLOCK: 32K->128K, aligned with other ARM boards.
- Preserve RW_DDR_TRAINING for new calibration.
- Reorder the sections for better alignment.
- RW_MISC to contain RW sections that should be merged when creating AU image.

BUG=b:134624821
TEST=Built Kukui image and boots. dump_fmap -h image-kukui.bin:
     # name              start       end         size
     RW_LEGACY           00700000    00800000    00100000
     RW_SHARED           006f7000    00700000    00009000
       RW_UNUSED           006f8000    00700000    00008000
       SHARED_DATA         006f7000    006f8000    00001000
     RW_SECTION_B        00580000    006f7000    00177000
       RW_FWID_B           006f6f00    006f7000    00000100
       FW_MAIN_B           00582000    006f6f00    00174f00
       VBLOCK_B            00580000    00582000    00002000
     RW_MISC             00577000    00580000    00009000
       RW_ELOG             0057f000    00580000    00001000
       RW_DDR_TRAINING     0057d000    0057f000    00002000
       RW_NVRAM            0057b000    0057d000    00002000
       RW_VPD              00577000    0057b000    00004000
     RW_SECTION_A        00400000    00577000    00177000
       RW_FWID_A           00576f00    00577000    00000100
       FW_MAIN_A           00402000    00576f00    00174f00
       VBLOCK_A            00400000    00402000    00002000
     WP_RO               00000000    00400000    00400000
       RO_VPD              003f8000    00400000    00008000
       RO_SECTION          00000000    003f8000    003f8000
         RO_FRID             003f7f00    003f8000    00000100
         GBB                 003f5000    003f7f00    00002f00
         COREBOOT            00021000    003f5000    003d4000
         FMAP                00020000    00021000    00001000
         BOOTBLOCK           00000000    00020000    00020000

Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-04 16:25:56 +00:00
3rdparty Update arm-trusted-firmware submodule to upstream master 2019-10-03 18:30:08 +00:00
Documentation mb/supermicro/x11-lga1151-series: rework documentation 2019-10-04 16:24:59 +00:00
configs configs: Build test CONFIG_BOOTSPLASH 2019-09-27 16:20:16 +00:00
payloads libpayload: refactor fetching cbmem pointers 2019-10-03 15:27:30 +00:00
src mb/google/kukui: Extend FMAP to 8MB layout 2019-10-04 16:25:56 +00:00
util ifdtool: Add validate option to ifdtool 2019-10-03 15:28:15 +00:00
.checkpatch.conf
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore util/bucts: Add tool to manipulate BUC.TS bit on Intel targets 2018-11-19 08:19:16 +00:00
.gitmodules 3rdparty/ffs: add open-power ffs utils 2019-08-25 07:37:11 +00:00
.gitreview
AUTHORS AUTHORS: Move src/device copyrights into AUTHORS file 2019-09-17 08:14:13 +00:00
COPYING
MAINTAINERS MAINTAINERS: Step down as RISC-V maintainer 2019-08-05 22:43:36 +00:00
Makefile coreboot/Makefile: display error when spaces in path of toplevel makefile 2019-09-26 10:11:14 +00:00
Makefile.inc Makefile: Create the build directory before bootblock.bin 2019-09-24 10:36:24 +00:00
README.md README: Convert to Markdown 2018-09-16 13:01:58 +00:00
gnat.adc
toolchain.inc Split MAYBE_STATIC to _BSS and _NONZERO variants 2019-08-26 20:56:29 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.