b78c1972fe
be in place but don't expect anything to quite work yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
108 lines
3 KiB
C
108 lines
3 KiB
C
/*
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This software and ancillary information (herein called SOFTWARE )
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called LinuxBIOS is made available under the terms described
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here. The SOFTWARE has been approved for release with associated
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LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
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been authored by an employee or employees of the University of
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California, operator of the Los Alamos National Laboratory under
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Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
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U.S. Government has rights to use, reproduce, and distribute this
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SOFTWARE. The public may copy, distribute, prepare derivative works
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and publicly display this SOFTWARE without charge, provided that this
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Notice and any statement of authorship are reproduced on all copies.
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Neither the Government nor the University makes any warranty, express
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or implied, or assumes any liability or responsibility for the use of
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this SOFTWARE. If SOFTWARE is modified to produce derivative works,
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such modified SOFTWARE should be clearly marked, so as not to confuse
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it with the version available from LANL.
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*/
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/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
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* rminnich@lanl.gov
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*/
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/*
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* C Bootstrap code for the LinuxBIOS
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*/
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#include <console/console.h>
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#include <mem.h>
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#include <version.h>
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#include <boot/tables.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/chip.h>
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#include <delay.h>
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#include <stdlib.h>
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#include <part/hard_reset.h>
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#include <boot/elf.h>
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void hardwaremain(int boot_complete)
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{
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/* the order here is a bit tricky. We don't want to do much of
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* anything that uses config registers until after PciAllocateResources
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* since that function also figures out what kind of config strategy
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* to use (type 1 or type 2).
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* so we turn on cache, then worry about PCI setup, then do other
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* things, so that the other work can use the PciRead* and PciWrite*
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* functions.
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*/
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struct lb_memory *lb_mem;
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post_code(0x80);
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CONFIGURE(CONF_PASS_PRE_CONSOLE);
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/* displayinit MUST PRECEDE ALL PRINTK! */
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console_init();
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post_code(0x39);
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printk_notice("LinuxBIOS-%s%s %s %s...\n",
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linuxbios_version, linuxbios_extra_version, linuxbios_build,
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(boot_complete)?"rebooting":"booting");
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post_code(0x40);
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/* If we have already booted attempt a hard reboot */
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if (boot_complete) {
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hard_reset();
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}
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CONFIGURE(CONF_PASS_PRE_PCI);
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/* pick how to scan the bus. This is first so we can get at memory size. */
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printk_info("Finding PCI configuration type.\n");
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pci_set_method();
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post_code(0x5f);
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enumerate_static_devices();
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dev_enumerate();
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post_code(0x66);
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/* Now do the real bus.
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* We round the total ram up a lot for thing like the SISFB, which
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* shares high memory with the CPU.
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*/
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dev_configure();
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post_code(0x88);
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dev_enable();
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dev_initialize();
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post_code(0x89);
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CONFIGURE(CONF_PASS_POST_PCI);
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/* Now that we have collected all of our information
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* write our configuration tables.
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*/
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lb_mem = write_tables();
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CONFIGURE(CONF_PASS_PRE_BOOT);
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#if CONFIG_FS_STREAM == 1
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filo(lb_mem);
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#else
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elfboot(lb_mem);
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#endif
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}
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