228aae589c
Disable kepler device, it is removed and was not used on proto anyway. BUG=none BRANCH=none TEST=build and boot on lars proto Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1 Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315950 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12950 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
135 lines
4.7 KiB
Text
135 lines
4.7 KiB
Text
chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s3_enable" = "0"
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register "deep_s5_enable" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command range is in 0x800-0x8ff
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register "gen1_dec" = "0x00fc0801"
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# Enable DPTF
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register "dptf_enable" = "1"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "2"
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register "IshEnable" = "0"
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register "PttSwitch" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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# Enable Root port 1.
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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# RP 1 uses SRCCLKREQ1#
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register "PcieRpClkReqNumber[0]" = "1"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
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register "usb2_ports[1]" = "USB2_PORT_FLEX" # Camera
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register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
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register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card)
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register "usb2_ports[5]" = "USB2_PORT_MID" # SD
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register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board)
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{ \
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[PchSerialIoIndexI2C0] = PchSerialIoPci, \
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[PchSerialIoIndexI2C1] = PchSerialIoPci, \
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C4] = PchSerialIoPci, \
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart0] = PchSerialIoPci, \
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[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 off end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # I2C #4
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device pci 1c.0 on end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1e.0 on end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1e.4 on end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 on end # SDCard
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC Interface
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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