a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
128 lines
2.9 KiB
C
128 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <elog.h>
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#include <ec/google/chromeec/ec.h>
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#include <soc/iomap.h>
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#include <soc/nvs.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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#include "ec.h"
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#include "gpio.h"
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int mainboard_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x99:
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printk(BIOS_DEBUG, "Sample\n");
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smm_get_gnvs()->smif = 0;
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break;
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default:
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return 0;
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}
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/* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*
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* For now, we force the return value to 0 and log all traps to
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* see what's going on.
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*/
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return 1;
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}
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static u8 mainboard_smi_ec(void)
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{
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u8 cmd = 0;
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#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
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u32 pm1_cnt;
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cmd = google_chromeec_get_event();
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/* Log this event */
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if (IS_ENABLED(CONFIG_ELOG_GSMI) && cmd)
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elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
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switch (cmd) {
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case EC_HOST_EVENT_LID_CLOSED:
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printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
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/* Go to S5 */
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pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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pm1_cnt |= (0xf << 10);
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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break;
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}
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#endif
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return cmd;
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}
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void mainboard_smi_gpi_handler(const struct gpi_status *sts)
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{
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if (gpi_status_get(sts, EC_SMI_GPI)) {
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/* Process all pending events */
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while (mainboard_smi_ec() != 0)
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;
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}
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}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
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switch (slp_typ) {
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case 3:
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
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break;
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case 5:
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
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break;
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}
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/* Disable SCI and SMI events */
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google_chromeec_set_smi_mask(0);
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google_chromeec_set_sci_mask(0);
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/* Clear pending events that may trigger immediate wake */
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while (google_chromeec_get_event() != 0)
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;
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#endif
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}
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int mainboard_smi_apmc(u8 apmc)
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{
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#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
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switch (apmc) {
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case APM_CNT_ACPI_ENABLE:
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google_chromeec_set_smi_mask(0);
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/* Clear all pending events */
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while (google_chromeec_get_event() != 0)
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;
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google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
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break;
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case APM_CNT_ACPI_DISABLE:
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google_chromeec_set_sci_mask(0);
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/* Clear all pending events */
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while (google_chromeec_get_event() != 0)
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;
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google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
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break;
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}
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#endif
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return 0;
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}
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