coreboot-kgpe-d16/src/soc/intel
Subrata Banik b7e69a2e56 Skylake: Support Intel Speed Shift Technology based on config
Intel Speed Shift Technology is a new mechanism that replaces
Legacy P-state. ISST allows OS hints about energy/performance
preference. H/W performs the actual P-state control (autonomous)

1. Optimization frequency seclection for low residency workloads,
no longer a static knee point.
2. Optimized frequency selection for best energy to performance
trade offs.
3. Kick down frequency (from idle) fpr best responsiveness while
taking energy consumption init account.

Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits
which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes
and enable HWP accordingly.

BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu and verify HWP getting enabled/disabled
using Intel P-state driver.

Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f
Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313107
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://review.coreboot.org/13835
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-01 20:57:45 +01:00
..
apollolake soc/intel/apollolake: implement bootblock_soc_early_init() 2016-02-26 02:17:32 +01:00
baytrail tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))" 2016-02-26 07:01:21 +01:00
braswell timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig 2016-02-12 21:54:52 +01:00
broadwell chromeos: Remove CONFIG_VBNV_SIZE variable 2016-02-09 13:19:48 +01:00
common soc/intel/common: Use SoC specific routine to read/write MTRRs 2016-02-02 19:00:35 +01:00
fsp_baytrail fsp_baytrail: Fix a possible hanging DisplayPort 2016-02-25 15:16:44 +01:00
quark soc/intel/quark: Reserve non-MMIO space 2016-02-29 05:00:27 +01:00
skylake Skylake: Support Intel Speed Shift Technology based on config 2016-03-01 20:57:45 +01:00