21961fc092
This includes a huge set of refactorings to support Core Display Clock (CDClk) frequency switching based on the current mode requirements. The CDClk is configurable since Haswell and runtime switching is suppor- ted since Broadwell. Always using the lowest possible frequency setting should allow some power-savings. While, on the upper end, we can support higher resolution panels now, without having to change the static confi- guration. There have also been some smaller changes and fixes, including: o Parsing of eDP 1.4+ DPCD link rates, enables panels that don't advertise a maximum link rate but only individual ones. o DP support for Ibex Peak. o Corrected limit for HDMI on G45 to 165MHz. o Reworked GMBUS reset handling and timeouts, should help with stalled GMBUS controllers when unimplemented ports were probed by accident. Tested on various boards from GM45 to KBL-R. Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35898 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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arm-trusted-firmware@ace23683be | ||
blobs@62aa0e0c54 | ||
chromeec@a1afae4e00 | ||
ffs@3ec70fbc45 | ||
fsp@59964173e1 | ||
intel-microcode@1dd14da6d1 | ||
libgfxinit@fe7985f2a0 | ||
libhwbase@bd0ed91cb9 | ||
opensbi@e561c63036 | ||
vboot@b2c8984d37 |