a6529e789f
These definitions were identical to picasso. The only thing I changed was that I renamed Misc1 and Misc2 to HPET_L and HPET_H. This change still doesn't write the PCI_IRQ register for all the PCI devices. We need to refactor the picasso pci_gpp code first. TEST=Boot majolica and see FCH IRQs being programmed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50451 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
131 lines
3.2 KiB
C
131 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/amd_pci_util.h>
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#include <amdblocks/smi.h>
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#include <assert.h>
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#include <bootstate.h>
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#include <cpu/x86/smm.h>
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#include <soc/amd_pci_int_defs.h>
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#include <soc/iomap.h>
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#include <soc/smi.h>
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#include <soc/southbridge.h>
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/*
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* Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
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* provides a visible association with the index, therefore helping
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* maintainability of table. If a new index/name is defined in
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* amd_pci_int_defs.h, just add the pair at the end of this table.
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* Order is not important.
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*/
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const static struct irq_idx_name irq_association[] = {
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{ PIRQ_A, "INTA#" },
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{ PIRQ_B, "INTB#" },
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{ PIRQ_C, "INTC#" },
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{ PIRQ_D, "INTD#" },
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{ PIRQ_E, "INTE#" },
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{ PIRQ_F, "INTF#/GENINT2" },
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{ PIRQ_G, "INTG#" },
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{ PIRQ_H, "INTH#" },
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{ PIRQ_MISC, "Misc" },
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{ PIRQ_MISC0, "Misc0" },
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{ PIRQ_HPET_L, "HPET_L" },
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{ PIRQ_HPET_H, "HPET_H" },
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{ PIRQ_SIRQA, "Ser IRQ INTA" },
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{ PIRQ_SIRQB, "Ser IRQ INTB" },
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{ PIRQ_SIRQC, "Ser IRQ INTC" },
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{ PIRQ_SIRQD, "Ser IRQ INTD" },
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{ PIRQ_SCI, "SCI" },
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{ PIRQ_SMBUS, "SMBUS" },
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{ PIRQ_ASF, "ASF" },
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{ PIRQ_PMON, "PerMon" },
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{ PIRQ_SD, "SD" },
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{ PIRQ_SDIO, "SDIO" },
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{ PIRQ_CIR, "CIR" },
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{ PIRQ_GPIOA, "GPIOa" },
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{ PIRQ_GPIOB, "GPIOb" },
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{ PIRQ_GPIOC, "GPIOc" },
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{ PIRQ_SATA, "SATA" },
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{ PIRQ_EMMC, "eMMC" },
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{ PIRQ_GPP0, "GPP0" },
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{ PIRQ_GPP1, "GPP1" },
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{ PIRQ_GPP2, "GPP2" },
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{ PIRQ_GPP3, "GPP3" },
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{ PIRQ_GPIO, "GPIO" },
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{ PIRQ_I2C0, "I2C0" },
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{ PIRQ_I2C1, "I2C1" },
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{ PIRQ_I2C2, "I2C2" },
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{ PIRQ_I2C3, "I2C3" },
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{ PIRQ_UART0, "UART0" },
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{ PIRQ_UART1, "UART1" },
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{ PIRQ_I2C4, "I2C4" },
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{ PIRQ_I2C5, "I2C5" },
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};
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const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
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{
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*size = ARRAY_SIZE(irq_association);
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return irq_association;
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}
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static void fch_init_acpi_ports(void)
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{
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u32 reg;
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/* We use some of these ports in SMM regardless of whether or not
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* ACPI tables are generated. Enable these ports indiscriminately.
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*/
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pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
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pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
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pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
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pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
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if (CONFIG(HAVE_SMI_HANDLER)) {
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/* APMC - SMI Command Port */
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pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
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configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
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/* SMI on SlpTyp requires sending SMI before completion
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response of the I/O write. */
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reg = pm_read32(PM_PCI_CTRL);
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reg |= FORCE_SLPSTATE_RETRY;
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pm_write32(PM_PCI_CTRL, reg);
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/* Disable SlpTyp feature */
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reg = pm_read8(PM_RST_CTRL1);
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reg &= ~SLPTYPE_CONTROL_EN;
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pm_write8(PM_RST_CTRL1, reg);
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configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
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} else {
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pm_write16(PM_ACPI_SMI_CMD, 0);
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}
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/* Decode ACPI registers and enable standard features */
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pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
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PM_ACPI_GLOBAL_EN |
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PM_ACPI_RTC_EN_EN |
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PM_ACPI_TIMER_EN_EN);
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}
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void fch_init(void *chip_info)
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{
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fch_init_acpi_ports();
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}
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void fch_final(void *chip_info)
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{
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}
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static void set_pci_irqs(void *unused)
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{
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/* Write PCI_INTR regs 0xC00/0xC01 */
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write_pci_int_table();
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}
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/*
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* Hook this function into the PCI state machine
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* on entry into BS_DEV_ENABLE.
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*/
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
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