b3162b5a38
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
76 lines
2.1 KiB
Text
76 lines
2.1 KiB
Text
## SPDX-License-Identifier: GPL-2.0-only
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chip soc/nvidia/tegra210
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device cpu_cluster 0 on
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device cpu 0 on end
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device cpu 1 on end
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device cpu 2 on end
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device cpu 3 on end
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end
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register "display_controller" = "TEGRA_ARM_DISPLAYA"
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register "xres" = "1366"
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register "yres" = "768"
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# framebuffer resolution
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register "display_xres" = "1368"
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register "display_yres" = "678"
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# bits per pixel and color depth
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register "framebuffer_bits_per_pixel" = "16"
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register "color_depth" = "6"
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register "panel_bits_per_pixel" = "18"
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# How to compute these: xrandr --verbose will give you this:
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#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
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# 2560 2608 2640 2720 hborder 0
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# 1700 1703 1713 1749 vborder 0
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#Then you can compute your values:
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#H front porch = 2608 - 2560 = 48
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#H sync = 2640 - 2608 = 32
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#H back porch = 2720 - 2640 = 80
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#V front porch = 1703 - 1700 = 3
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#V sync = 1713 - 1703 = 10
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#V back porch = 1749 - 1713 = 36
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#href_to_sync and vref_to_sync are from the vendor
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#this is just an example for a Pixel panel; other panels differ.
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# Here is a peppy panel:
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# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
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# h: width 1366 start 1502 end 1532 total 1592
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# v: height 768 start 776 end 788 total 800
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register "href_to_sync" = "1"
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register "hfront_porch" = "136"
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register "hsync_width" = "30"
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register "hback_porch" = "60"
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register "vref_to_sync" = "1"
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register "vfront_porch" = "8"
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register "vsync_width" = "12"
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register "vback_porch" = "12"
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register "pixel_clock" = "76400000"
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register "win_opt" = "SOR_ENABLE"
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#
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# dp specific fields
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#
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register "dp.pwm" = "1"
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# various panel delay time
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register "dp.vdd_to_hpd_delay_ms" = "200"
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register "dp.hpd_unplug_min_us" = "2000"
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register "dp.hpd_plug_min_us" = "250"
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register "dp.hpd_irq_min_us" = "250"
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# link configurations
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register "dp.lane_count" = "1"
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register "dp.enhanced_framing" = "1"
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register "dp.link_bw" = "10"
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# "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
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register "dp.drive_current" = "0x40404040"
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register "dp.preemphasis" = "0x0f0f0f0f"
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register "dp.postcursor" = "0"
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end
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