e0e784a456
Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
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702 B
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20 lines
702 B
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 Google, Inc.
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##
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## This software is licensed under the terms of the GNU General Public
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## License version 2, as published by the Free Software Foundation, and
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## may be copied, distributed, and modified under those terms.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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chip soc/ucb/riscv
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device cpu_cluster 0 on end
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chip drivers/generic/generic # I2C0 controller
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device i2c 6 on end # Fake component for testing
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end
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end
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