b890a1228d
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
684 lines
19 KiB
C
684 lines
19 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <types.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_def.h>
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#include <halt.h>
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#include <pc80/mc146818rtc.h>
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#include "i82801gx.h"
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/* I945 */
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#define SMRAM 0x9d
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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#define D_LCK (1 << 4)
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#define G_SMRANE (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#include "nvs.h"
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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*/
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u16 pmbase = DEFAULT_PMBASE;
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u8 smm_initialized = 0;
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/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
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* by coreboot.
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*/
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global_nvs_t *gnvs = (global_nvs_t *)0x0;
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static void alt_gpi_mask(u16 clr, u16 set)
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{
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u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
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alt_gp &= ~clr;
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alt_gp |= set;
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outw(alt_gp, pmbase + ALT_GP_SMI_EN);
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}
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static void gpe0_mask(u32 clr, u32 set)
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{
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u32 gpe0 = inl(pmbase + GPE0_EN);
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gpe0 &= ~clr;
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gpe0 |= set;
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outl(gpe0, pmbase + GPE0_EN);
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}
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void gpi_route_interrupt(u8 gpi, u8 mode)
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{
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u32 gpi_rout;
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if (gpi >= 16)
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return;
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alt_gpi_mask(1 << gpi, 0);
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gpe0_mask(1 << (gpi+16), 0);
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gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
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gpi_rout &= ~(3 << (2 * gpi));
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gpi_rout |= ((mode & 3) << (2 * gpi));
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pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);
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if (mode == GPI_IS_SCI)
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gpe0_mask(0, 1 << (gpi+16));
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else if (mode == GPI_IS_SMI)
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alt_gpi_mask(0, 1 << gpi);
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}
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/**
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* @brief read and clear PM1_STS
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* @return PM1_STS register
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*/
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static u16 reset_pm1_status(void)
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{
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u16 reg16;
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reg16 = inw(pmbase + PM1_STS);
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/* set status bits are cleared by writing 1 to them */
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outw(reg16, pmbase + PM1_STS);
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return reg16;
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}
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static void dump_pm1_status(u16 pm1_sts)
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{
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printk(BIOS_SPEW, "PM1_STS: ");
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if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
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if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
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if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
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if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
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if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
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if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
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if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
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if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
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printk(BIOS_SPEW, "\n");
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int reg16 = inw(pmbase + PM1_EN);
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printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
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}
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/**
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* @brief read and clear SMI_STS
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* @return SMI_STS register
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*/
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static u32 reset_smi_status(void)
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{
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u32 reg32;
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reg32 = inl(pmbase + SMI_STS);
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/* set status bits are cleared by writing 1 to them */
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outl(reg32, pmbase + SMI_STS);
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return reg32;
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}
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static void dump_smi_status(u32 smi_sts)
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{
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printk(BIOS_DEBUG, "SMI_STS: ");
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if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
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if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
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if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
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if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
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if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
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if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
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if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
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if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
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if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
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if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
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if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
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if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
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if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
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if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
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if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
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if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
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if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
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if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
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if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
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if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear GPE0_STS
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* @return GPE0_STS register
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*/
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static u32 reset_gpe0_status(void)
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{
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u32 reg32;
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reg32 = inl(pmbase + GPE0_STS);
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/* set status bits are cleared by writing 1 to them */
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outl(reg32, pmbase + GPE0_STS);
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return reg32;
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}
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static void dump_gpe0_status(u32 gpe0_sts)
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{
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int i;
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printk(BIOS_DEBUG, "GPE0_STS: ");
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for (i=31; i>= 16; i--) {
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if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
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}
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if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
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if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
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if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
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if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
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if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
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if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
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if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
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if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
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if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
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if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
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if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
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if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
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if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
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if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear TCOx_STS
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* @return TCOx_STS registers
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*/
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static u32 reset_tco_status(void)
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{
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u32 tcobase = pmbase + 0x60;
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u32 reg32;
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reg32 = inl(tcobase + 0x04);
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/* set status bits are cleared by writing 1 to them */
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outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
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if (reg32 & (1 << 18))
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outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
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return reg32;
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}
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static void dump_tco_status(u32 tco_sts)
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{
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printk(BIOS_DEBUG, "TCO_STS: ");
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if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
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if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
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if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
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if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
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if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
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if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
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if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
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if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
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if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
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if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
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if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
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if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
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if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
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printk(BIOS_DEBUG, "\n");
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}
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/* We are using PCIe accesses for now
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* 1. the chipset can do it
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* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
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*/
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#include <arch/pci_mmio_cfg.h>
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int southbridge_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x32:
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printk(BIOS_DEBUG, "OS Init\n");
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/* gnvs->smif:
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* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*/
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gnvs->smif = 0;
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return 1; /* IO trap handled */
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}
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/* Not handled */
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return 0;
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}
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/**
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* @brief Set the EOS bit
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*/
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void southbridge_smi_set_eos(void)
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{
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u8 reg8;
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reg8 = inb(pmbase + SMI_EN);
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reg8 |= EOS;
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outb(reg8, pmbase + SMI_EN);
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}
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static void busmaster_disable_on_bus(int bus)
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{
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int slot, func;
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unsigned int val;
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unsigned char hdr;
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for (slot = 0; slot < 0x20; slot++) {
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for (func = 0; func < 8; func++) {
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u32 reg32;
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device_t dev = PCI_DEV(bus, slot, func);
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val = pci_read_config32(dev, PCI_VENDOR_ID);
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if (val == 0xffffffff || val == 0x00000000 ||
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val == 0x0000ffff || val == 0xffff0000)
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continue;
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/* Disable Bus Mastering for this one device */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 &= ~PCI_COMMAND_MASTER;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* If this is a bridge, then follow it. */
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hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
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hdr &= 0x7f;
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if (hdr == PCI_HEADER_TYPE_BRIDGE ||
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hdr == PCI_HEADER_TYPE_CARDBUS) {
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unsigned int buses;
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buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
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busmaster_disable_on_bus((buses >> 8) & 0xff);
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}
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}
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}
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}
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static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
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{
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u8 reg8;
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u32 reg32;
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u8 slp_typ;
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u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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// save and recover RTC port values
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u8 tmp70, tmp72;
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tmp70 = inb(0x70);
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tmp72 = inb(0x72);
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get_option(&s5pwr, "power_on_after_fail");
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outb(tmp70, 0x70);
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outb(tmp72, 0x72);
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/* First, disable further SMIs */
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reg8 = inb(pmbase + SMI_EN);
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reg8 &= ~SLP_SMI_EN;
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outb(reg8, pmbase + SMI_EN);
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/* Figure out SLP_TYP */
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reg32 = inl(pmbase + PM1_CNT);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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slp_typ = (reg32 >> 10) & 7;
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/* Next, do the deed.
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*/
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switch (slp_typ) {
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case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
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case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
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case 5:
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printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
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/* Invalidate the cache before going to S3 */
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wbinvd();
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break;
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case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
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case 7:
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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outl(0, pmbase + GPE0_EN);
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/* Always set the flag in case CMOS was changed on runtime. For
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* "KEEP", switch to "OFF" - KEEP is software emulated
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*/
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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if (s5pwr == MAINBOARD_POWER_ON) {
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reg8 &= ~1;
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} else {
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reg8 |= 1;
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}
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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break;
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default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
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}
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#if !CONFIG_SMM_TSEG
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/* Unlock the SMI semaphore. We're currently in SMM, and the semaphore
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* will never be unlocked because the next outl will switch off the CPU.
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* This might open a small race between the smi_release_lock() and the outl()
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* for other SMI handlers. Not sure if this could cause trouble. */
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if (slp_typ == 5)
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smi_release_lock();
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#endif
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/* Write back to the SLP register to cause the originally intended
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* event again. We need to set BIT13 (SLP_EN) though to make the
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* sleep happen.
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*/
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outl(reg32 | SLP_EN, pmbase + PM1_CNT);
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/* Make sure to stop executing code here for S3/S4/S5 */
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if (slp_typ > 1)
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halt();
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/* In most sleep states, the code flow of this function ends at
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* the line above. However, if we entered sleep state S1 and wake
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* up again, we will continue to execute code in this function.
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*/
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reg32 = inl(pmbase + PM1_CNT);
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if (reg32 & SCI_EN) {
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/* The OS is not an ACPI OS, so we set the state to S0 */
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reg32 &= ~(SLP_EN | SLP_TYP);
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outl(reg32, pmbase + PM1_CNT);
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}
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}
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static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
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{
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u32 pmctrl;
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u8 reg8;
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/* Emulate B2 register as the FADT / Linux expects it */
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reg8 = inb(APM_CNT);
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if (mainboard_smi_apmc(reg8))
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return;
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switch (reg8) {
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case APM_CNT_CST_CONTROL:
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/* Calling this function seems to cause
|
||
* some kind of race condition in Linux
|
||
* and causes a kernel oops
|
||
*/
|
||
printk(BIOS_DEBUG, "C-state control\n");
|
||
break;
|
||
case APM_CNT_PST_CONTROL:
|
||
/* Calling this function seems to cause
|
||
* some kind of race condition in Linux
|
||
* and causes a kernel oops
|
||
*/
|
||
printk(BIOS_DEBUG, "P-state control\n");
|
||
break;
|
||
case APM_CNT_ACPI_DISABLE:
|
||
pmctrl = inl(pmbase + PM1_CNT);
|
||
pmctrl &= ~SCI_EN;
|
||
outl(pmctrl, pmbase + PM1_CNT);
|
||
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
|
||
break;
|
||
case APM_CNT_ACPI_ENABLE:
|
||
pmctrl = inl(pmbase + PM1_CNT);
|
||
pmctrl |= SCI_EN;
|
||
outl(pmctrl, pmbase + PM1_CNT);
|
||
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
|
||
break;
|
||
case APM_CNT_GNVS_UPDATE:
|
||
if (smm_initialized) {
|
||
printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
|
||
return;
|
||
}
|
||
gnvs = *(global_nvs_t **)0x500;
|
||
smm_initialized = 1;
|
||
printk(BIOS_DEBUG, "SMI#: Setting up structures to %p\n", gnvs);
|
||
break;
|
||
default:
|
||
printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
|
||
}
|
||
}
|
||
|
||
static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
|
||
{
|
||
u16 pm1_sts;
|
||
volatile u8 cmos_status;
|
||
|
||
pm1_sts = reset_pm1_status();
|
||
dump_pm1_status(pm1_sts);
|
||
|
||
/* While OSPM is not active, poweroff immediately
|
||
* on a power button event.
|
||
*/
|
||
if (pm1_sts & PWRBTN_STS) {
|
||
// power button pressed
|
||
u32 reg32;
|
||
reg32 = (7 << 10) | (1 << 13);
|
||
outl(reg32, pmbase + PM1_CNT);
|
||
}
|
||
|
||
if (pm1_sts & RTC_STS) {
|
||
/* read RTC status register to disable the interrupt */
|
||
cmos_status = cmos_read(RTC_REG_C);
|
||
printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status);
|
||
}
|
||
}
|
||
|
||
static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
|
||
{
|
||
u32 gpe0_sts;
|
||
|
||
gpe0_sts = reset_gpe0_status();
|
||
dump_gpe0_status(gpe0_sts);
|
||
}
|
||
|
||
static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
|
||
{
|
||
u16 reg16;
|
||
reg16 = inw(pmbase + ALT_GP_SMI_STS);
|
||
outw(reg16, pmbase + ALT_GP_SMI_STS);
|
||
|
||
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
|
||
|
||
mainboard_smi_gpi(reg16);
|
||
|
||
if (reg16)
|
||
printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
|
||
}
|
||
|
||
static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
|
||
{
|
||
u32 reg32;
|
||
|
||
reg32 = inl(pmbase + SMI_EN);
|
||
|
||
/* Are periodic SMIs enabled? */
|
||
if ((reg32 & MCSMI_EN) == 0)
|
||
return;
|
||
|
||
printk(BIOS_DEBUG, "Microcontroller SMI.\n");
|
||
}
|
||
|
||
|
||
|
||
static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
|
||
{
|
||
u32 tco_sts;
|
||
|
||
tco_sts = reset_tco_status();
|
||
|
||
/* Any TCO event? */
|
||
if (!tco_sts)
|
||
return;
|
||
|
||
if (tco_sts & (1 << 8)) { // BIOSWR
|
||
u8 bios_cntl;
|
||
|
||
bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
|
||
|
||
if (bios_cntl & 1) {
|
||
/* BWE is RW, so the SMI was caused by a
|
||
* write to BWE, not by a write to the BIOS
|
||
*/
|
||
|
||
/* This is the place where we notice someone
|
||
* is trying to tinker with the BIOS. We are
|
||
* trying to be nice and just ignore it. A more
|
||
* resolute answer would be to power down the
|
||
* box.
|
||
*/
|
||
printk(BIOS_DEBUG, "Switching back to RO\n");
|
||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
|
||
} /* No else for now? */
|
||
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
|
||
/* Handle TCO timeout */
|
||
printk(BIOS_DEBUG, "TCO Timeout.\n");
|
||
} else if (!tco_sts) {
|
||
dump_tco_status(tco_sts);
|
||
}
|
||
}
|
||
|
||
static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
|
||
{
|
||
u32 reg32;
|
||
|
||
reg32 = inl(pmbase + SMI_EN);
|
||
|
||
/* Are periodic SMIs enabled? */
|
||
if ((reg32 & PERIODIC_EN) == 0)
|
||
return;
|
||
|
||
printk(BIOS_DEBUG, "Periodic SMI.\n");
|
||
}
|
||
|
||
static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
|
||
{
|
||
#define IOTRAP(x) (trap_sts & (1 << x))
|
||
u32 trap_sts, trap_cycle;
|
||
u32 data, mask = 0;
|
||
int i;
|
||
|
||
trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
|
||
RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
|
||
|
||
trap_cycle = RCBA32(0x1e10);
|
||
for (i=16; i<20; i++) {
|
||
if (trap_cycle & (1 << i))
|
||
mask |= (0xff << ((i - 16) << 2));
|
||
}
|
||
|
||
|
||
/* IOTRAP(3) SMI function call */
|
||
if (IOTRAP(3)) {
|
||
if (gnvs && gnvs->smif)
|
||
io_trap_handler(gnvs->smif); // call function smif
|
||
return;
|
||
}
|
||
|
||
/* IOTRAP(2) currently unused
|
||
* IOTRAP(1) currently unused */
|
||
|
||
/* IOTRAP(0) SMIC: currently unused */
|
||
|
||
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
|
||
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
|
||
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
|
||
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
|
||
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
|
||
|
||
if (!(trap_cycle & (1 << 24))) {
|
||
/* Write Cycle */
|
||
data = RCBA32(0x1e18);
|
||
printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
|
||
}
|
||
#undef IOTRAP
|
||
}
|
||
|
||
typedef void (*smi_handler_t)(unsigned int node,
|
||
smm_state_save_area_t *state_save);
|
||
|
||
smi_handler_t southbridge_smi[32] = {
|
||
NULL, // [0] reserved
|
||
NULL, // [1] reserved
|
||
NULL, // [2] BIOS_STS
|
||
NULL, // [3] LEGACY_USB_STS
|
||
southbridge_smi_sleep, // [4] SLP_SMI_STS
|
||
southbridge_smi_apmc, // [5] APM_STS
|
||
NULL, // [6] SWSMI_TMR_STS
|
||
NULL, // [7] reserved
|
||
southbridge_smi_pm1, // [8] PM1_STS
|
||
southbridge_smi_gpe0, // [9] GPE0_STS
|
||
southbridge_smi_gpi, // [10] GPI_STS
|
||
southbridge_smi_mc, // [11] MCSMI_STS
|
||
NULL, // [12] DEVMON_STS
|
||
southbridge_smi_tco, // [13] TCO_STS
|
||
southbridge_smi_periodic, // [14] PERIODIC_STS
|
||
NULL, // [15] SERIRQ_SMI_STS
|
||
NULL, // [16] SMBUS_SMI_STS
|
||
NULL, // [17] LEGACY_USB2_STS
|
||
NULL, // [18] INTEL_USB2_STS
|
||
NULL, // [19] reserved
|
||
NULL, // [20] PCI_EXP_SMI_STS
|
||
southbridge_smi_monitor, // [21] MONITOR_STS
|
||
NULL, // [22] reserved
|
||
NULL, // [23] reserved
|
||
NULL, // [24] reserved
|
||
NULL, // [25] EL_SMI_STS
|
||
NULL, // [26] SPI_STS
|
||
NULL, // [27] reserved
|
||
NULL, // [28] reserved
|
||
NULL, // [29] reserved
|
||
NULL, // [30] reserved
|
||
NULL // [31] reserved
|
||
};
|
||
|
||
/**
|
||
* @brief Interrupt handler for SMI#
|
||
* @param node
|
||
* @param state_save
|
||
*/
|
||
|
||
void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
|
||
{
|
||
int i, dump = 0;
|
||
u32 smi_sts;
|
||
|
||
/* Update global variable pmbase */
|
||
pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
|
||
|
||
/* We need to clear the SMI status registers, or we won't see what's
|
||
* happening in the following calls.
|
||
*/
|
||
smi_sts = reset_smi_status();
|
||
|
||
/* Filter all non-enabled SMI events */
|
||
// FIXME Double check, this clears MONITOR
|
||
// smi_sts &= inl(pmbase + SMI_EN);
|
||
|
||
/* Call SMI sub handler for each of the status bits */
|
||
for (i = 0; i < 31; i++) {
|
||
if (smi_sts & (1 << i)) {
|
||
if (southbridge_smi[i])
|
||
southbridge_smi[i](node, state_save);
|
||
else {
|
||
printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
|
||
"handler available.\n", i);
|
||
dump = 1;
|
||
}
|
||
}
|
||
}
|
||
|
||
if(dump) {
|
||
dump_smi_status(smi_sts);
|
||
}
|
||
|
||
}
|