0867062412
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
104 lines
3 KiB
C
104 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 AMD
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* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ASSEMBLY 1
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#define __ROMCC__
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#define RAMINIT_SYSINFO 1
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#define CACHE_AS_RAM_ADDRESS_DEBUG 0
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#define SET_NB_CFG_54 1 /* Used by RAM init. */
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#define QRANK_DIMM_SUPPORT 1
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#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#if CONFIG_USE_INIT == 0
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#include "lib/memcpy.c"
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#endif
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#include "arch/i386/lib/console.c"
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#include <cpu/amd/model_fxx_rev.h>
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#include "lib/delay.c"
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/* #include "cpu/x86/lapic/boot_cpu.c" */
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
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#include "northbridge/amd/amdk8/amdk8_f.h"
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#include "cpu/x86/mtrr.h"
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#include "cpu/amd/mtrr.h"
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#include "cpu/x86/tsc.h"
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#include "northbridge/amd/amdk8/amdk8_f_pci.c"
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#include "northbridge/amd/amdk8/raminit_f_dqs.c"
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#include "cpu/amd/dualcore/dualcore.c"
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void hardwaremain(int ret_addr)
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{
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struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
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CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */
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struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK << 10) -
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CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */
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struct node_core_id id;
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id = get_node_core_id_x();
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/* FIXME: For USBDEBUG_DIRECT you need to make sure dbg_info gets
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* assigned in AP.
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*/
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print_debug("CODE IN CACHE ON NODE:");
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print_debug_hex8(id.nodeid);
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print_debug("\r\n");
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train_ram(id.nodeid, sysinfo, sysinfox);
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/* Go back, but cannot use stack any more, because we only
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* keep ret_addr and can not restore esp, and ebp.
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*/
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__asm__ __volatile__(
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"movl %0, %%edi\n\t"
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"jmp *%%edi\n\t"
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: : "a" (ret_addr)
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);
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}
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struct eregs {
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uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
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uint32_t vector;
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uint32_t error_code;
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uint32_t eip;
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uint32_t cs;
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uint32_t eflags;
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};
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void x86_exception(struct eregs *info)
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{
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while (1)
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hlt();
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}
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