b8e2027be8
to build, but by default all the tables that are available are built. Make PIRQ table build for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
265 lines
7.6 KiB
Text
265 lines
7.6 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Advanced Micro Devices, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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##
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##
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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default CONFIG_XIP_ROM_SIZE = 64 * 1024
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include /config/nofailovercalculation.lb
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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#dir /drivers/si/3114
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if CONFIG_GENERATE_MP_TABLE object mptable.o end
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if CONFIG_GENERATE_PIRQ_TABLE
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object get_bus_conf.o
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object irq_tables.o
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end
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if CONFIG_GENERATE_ACPI_TABLES
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object acpi_tables.o
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object fadt.o
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makerule dsdt.c
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depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
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action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
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action "mv dsdt.hex dsdt.c"
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end
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object ./dsdt.o
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end
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#object reset.o
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if CONFIG_USE_INIT
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makerule ./cache_as_ram_auto.o
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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end
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else
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makerule ./cache_as_ram_auto.inc
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/amd/car/cache_as_ram.inc
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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if CONFIG_USE_INIT
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initobject cache_as_ram_auto.o
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else
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mainboardinit ./cache_as_ram_auto.inc
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end
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##
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## Include the secondary Configuration files
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##
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config chip.h
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#The variables belong to mainboard are defined here.
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define vga_rom_address = 0xfff80000
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
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# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
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#Define gfx_dual_slot, 0: single slot, 1: dual slot
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#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
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#Define gfx_tmds, 0: didn't support TMDS, 1: support
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#Define gfx_compliance, 0: didn't support compliance, 1: support
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#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
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#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_S1G1
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8
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device pci 18.0 on # southbridge
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chip southbridge/amd/rs690
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device pci 0.0 on end # HT 0x7910
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device pci 1.0 on # Internal Graphics P2P bridge 0x7912
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chip drivers/pci/onboard
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device pci 5.0 on end # Internal Graphics 0x791F
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register "rom_address" = "0xfff80000"
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end
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end
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device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
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device pci 3.0 off end # PCIE P2P bridge 0x791b
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device pci 4.0 on end # PCIE P2P bridge 0x7914
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device pci 5.0 on end # PCIE P2P bridge 0x7915
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device pci 6.0 on end # PCIE P2P bridge 0x7916
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device pci 7.0 on end # PCIE P2P bridge 0x7917
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device pci 8.0 off end # NB/SB Link P2P bridge
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register "vga_rom_address" = "0xfff80000"
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register "gpp_configuration" = "4"
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register "port_enable" = "0xfc"
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register "gfx_dev2_dev3" = "1"
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register "gfx_dual_slot" = "0"
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register "gfx_lane_reversal" = "0"
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register "gfx_tmds" = "0"
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register "gfx_compliance" = "0"
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register "gfx_reconfiguration" = "1"
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register "gfx_link_width" = "0"
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end
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chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
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device pci 12.0 on end # SATA 0x4380
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device pci 13.0 on end # USB 0x4387
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device pci 13.1 on end # USB 0x4388
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device pci 13.2 on end # USB 0x4389
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device pci 13.3 on end # USB 0x438a
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device pci 13.4 on end # USB 0x438b
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device pci 13.5 on end # USB 2 0x4386
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device pci 14.0 on # SM 0x4385
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 0-1-1
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device i2c 53 on end
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end
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end # SM
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device pci 14.1 on end # IDE 0x438c
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on # LPC 0x438d
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chip superio/ite/it8712f
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 off end # EC
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # Mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
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end
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device pnp 2e.8 off # MIDI
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io 0x60 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.9 off # GAME
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io 0x60 = 0x220
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end
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device pnp 2e.a off end # CIR
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end #superio/ite/it8712f
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end #LPC
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device pci 14.4 on end # PCI 0x4384
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device pci 14.5 on end # ACI 0x4382
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device pci 14.6 on end # MCI 0x438e
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register "ide0_enable" = "1"
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register "sata0_enable" = "1"
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register "hda_viddid" = "0x10ec0882"
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end #southbridge/amd/sb600
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end # device pci 18.0
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end #northbridge/amd/amdk8
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end #pci_domain
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end #northbridge/amd/amdk8/root_complex
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