24f73d4f53
Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
901 lines
26 KiB
C
901 lines
26 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* ROMSIG At ROMBASE + 0x20000:
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* 0 4 8 C
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* +------------+---------------+----------------+------------+
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* | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
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* +------------+---------------+----------------+------------+
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* | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either
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* +------------+---------------+ 2nd PSP directory or PSP COMBO directory
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* EC ROM should be 64K aligned.
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*
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* PSP directory (Where "PSPDIR ADDR" points)
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* +------------+---------------+----------------+------------+
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* | 'PSP$' | Fletcher | Count | Reserved |
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* +------------+---------------+----------------+------------+
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* | 0 | size | Base address | Reserved | Pubkey
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* +------------+---------------+----------------+------------+
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* | 1 | size | Base address | Reserved | Bootloader
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* +------------+---------------+----------------+------------+
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* | 8 | size | Base address | Reserved | Smu Firmware
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* +------------+---------------+----------------+------------+
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* | 3 | size | Base address | Reserved | Recovery Firmware
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* +------------+---------------+----------------+------------+
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* | |
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* | |
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* | Other PSP Firmware |
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* | |
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* | |
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* +------------+---------------+----------------+------------+
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*
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* PSP Combo directory
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* +------------+---------------+----------------+------------+
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* | 'PSP2' | Fletcher | Count |Look up mode|
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* +------------+---------------+----------------+------------+
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* | R e s e r v e d |
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* +------------+---------------+----------------+------------+
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* | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory
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* +------------+---------------+----------------+------------+
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* | ID-Sel | PSP ID | PSPDIR ADDR | | 3rd PSP directory
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* +------------+---------------+----------------+------------+
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* | |
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* | Other PSP |
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* | |
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* +------------+---------------+----------------+------------+
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*
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*/
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#include <fcntl.h>
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#include <errno.h>
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#include <stdio.h>
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#include <sys/stat.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include <string.h>
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#include <stdlib.h>
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#include <getopt.h>
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#ifndef CONFIG_ROM_SIZE
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#define CONFIG_ROM_SIZE 0x400000
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#endif
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#define AMD_ROMSIG_OFFSET 0x20000
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#define MIN_ROM_KB 256
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#define ALIGN(val, by) (((val) + (by) - 1) & ~((by) - 1))
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#define _MAX(A, B) (((A) > (B)) ? (A) : (B))
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#define ERASE_ALIGNMENT 0x1000U
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#define TABLE_ALIGNMENT 0x1000U
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#define BLOB_ALIGNMENT 0x100U
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#define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT)
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#define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT)
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#define DEFAULT_SOFT_FUSE_CHAIN "0x1"
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#define EMBEDDED_FW_SIGNATURE 0x55aa55aa
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#define PSP_COOKIE 0x50535024 /* 'PSP$' */
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#define PSPL2_COOKIE 0x324c5024 /* '2LP$' */
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#define PSP2_COOKIE 0x50535032 /* 'PSP2' */
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/*
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* Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP
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* can support an optional "combo" implementation. If the PSP sees the
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* PSP2 cookie, it interprets the table as a roadmap to additional PSP
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* tables. Using this, support for multiple product generations may be
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* built into one image. If the PSP$ cookie is found, the table is a
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* normal directory table.
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*
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* Modern generations supporting the combo directories require the
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* pointer to be at offset 0x14 of the Embedded Firmware Structure,
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* regardless of the type of directory used. The --combo-capable
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* argument enforces this placement.
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*
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* TODO: Future work may require fully implementing the PSP_COMBO feature.
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*/
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#define PSP_COMBO 0
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typedef unsigned long long int uint64_t;
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typedef unsigned int uint32_t;
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typedef unsigned char uint8_t;
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typedef unsigned short uint16_t;
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/*
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* Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3.
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* The checksum field of the passed PDU does not need to be reset to zero.
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*
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* The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of
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* Lawrence Livermore Labs. The Fletcher Checksum was proposed as an
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* alternative to cyclical redundancy checks because it provides error-
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* detection properties similar to cyclical redundancy checks but at the
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* cost of a simple summation technique. Its characteristics were first
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* published in IEEE Transactions on Communications in January 1982. One
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* version has been adopted by ISO for use in the class-4 transport layer
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* of the network protocol.
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*
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* This program expects:
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* stdin: The input file to compute a checksum for. The input file
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* not be longer than 256 bytes.
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* stdout: Copied from the input file with the Fletcher's Checksum
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* inserted 8 bytes after the beginning of the file.
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* stderr: Used to print out error messages.
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*/
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static uint32_t fletcher32(const void *data, int length)
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{
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uint32_t c0;
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uint32_t c1;
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uint32_t checksum;
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int index;
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const uint16_t *pptr = data;
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length /= 2;
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c0 = 0xFFFF;
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c1 = 0xFFFF;
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for (index = 0; index < length; index++) {
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/*
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* Ignore the contents of the checksum field.
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*/
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c0 += *(pptr++);
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c1 += c0;
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if ((index % 360) == 0) {
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/* Sums[0,1] mod 64K + overflow */
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c0 = (c0 & 0xFFFF) + (c0 >> 16);
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c1 = (c1 & 0xFFFF) + (c1 >> 16);
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}
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}
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/* Sums[0,1] mod 64K + overflow */
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c0 = (c0 & 0xFFFF) + (c0 >> 16);
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c1 = (c1 & 0xFFFF) + (c1 >> 16);
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checksum = (c1 << 16) | c0;
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return checksum;
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}
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static void usage(void)
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{
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printf("amdfwtool: Create AMD Firmware combination\n");
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printf("Usage: amdfwtool [options] -f <size> -o <filename>\n");
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printf("-x | --xhci <FILE> Add XHCI blob\n");
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printf("-i | --imc <FILE> Add IMC blob\n");
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printf("-g | --gec <FILE> Add GEC blob\n");
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printf("\nPSP options:\n");
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printf("-A | --combo-capable Place PSP directory pointer at Embedded Firmware\n");
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printf(" offset able to support combo directory\n");
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printf("-M | --multilevel Generate primary and secondary tables\n");
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printf("-p | --pubkey <FILE> Add pubkey\n");
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printf("-b | --bootloader <FILE> Add bootloader\n");
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printf("-S | --subprogram <number> Sets subprogram field for the next firmware\n");
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printf("-s | --smufirmware <FILE> Add smufirmware\n");
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printf("-r | --recovery <FILE> Add recovery\n");
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printf("-k | --rtmpubkey <FILE> Add rtmpubkey\n");
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printf("-c | --secureos <FILE> Add secureos\n");
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printf("-n | --nvram <FILE> Add nvram\n");
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printf("-d | --securedebug <FILE> Add securedebug\n");
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printf("-t | --trustlets <FILE> Add trustlets\n");
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printf("-u | --trustletkey <FILE> Add trustletkey\n");
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printf("-w | --smufirmware2 <FILE> Add smufirmware2\n");
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printf("-m | --smuscs <FILE> Add smuscs\n");
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printf("-T | --soft-fuse <HEX_VAL> Override default soft fuse values\n");
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printf("\n-o | --output <filename> output filename\n");
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printf("-f | --flashsize <HEX_VAL> ROM size in bytes\n");
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printf(" size must be larger than %dKB\n",
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MIN_ROM_KB);
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printf(" and must a multiple of 1024\n");
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printf("-l | --location Location of Directory\n");
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printf("-h | --help show this help\n");
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}
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typedef enum _amd_fw_type {
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AMD_FW_PSP_PUBKEY = 0,
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AMD_FW_PSP_BOOTLOADER = 1,
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AMD_FW_PSP_SMU_FIRMWARE = 8,
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AMD_FW_PSP_RECOVERY = 3,
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AMD_FW_PSP_RTM_PUBKEY = 5,
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AMD_FW_PSP_SECURED_OS = 2,
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AMD_FW_PSP_NVRAM = 4,
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AMD_FW_PSP_SECURED_DEBUG = 9,
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AMD_FW_PSP_TRUSTLETS = 12,
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AMD_FW_PSP_TRUSTLETKEY = 13,
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AMD_FW_PSP_SMU_FIRMWARE2 = 18,
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AMD_PSP_FUSE_CHAIN = 11,
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AMD_FW_PSP_SMUSCS = 95,
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AMD_FW_L2_PTR = 0x40,
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AMD_FW_IMC,
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AMD_FW_GEC,
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AMD_FW_XHCI,
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AMD_FW_INVALID,
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} amd_fw_type;
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#define PSP_LVL1 0x1
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#define PSP_LVL2 0x2
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#define PSP_BOTH (PSP_LVL1 | PSP_LVL2)
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typedef struct _amd_fw_entry {
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amd_fw_type type;
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uint8_t subprog;
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char *filename;
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int level;
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uint64_t other;
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} amd_fw_entry;
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static amd_fw_entry amd_psp_fw_table[] = {
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{ .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 },
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{ .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 },
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{ .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 },
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{ .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 },
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{ .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH },
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{ .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH },
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{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH },
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{ .type = AMD_FW_INVALID },
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};
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static amd_fw_entry amd_fw_table[] = {
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{ .type = AMD_FW_XHCI },
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{ .type = AMD_FW_IMC },
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{ .type = AMD_FW_GEC },
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{ .type = AMD_FW_INVALID },
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};
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typedef struct _embedded_firmware {
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uint32_t signature; /* 0x55aa55aa */
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uint32_t imc_entry;
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uint32_t gec_entry;
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uint32_t xhci_entry;
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uint32_t psp_entry;
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uint32_t comboable;
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} __attribute__((packed, aligned(16))) embedded_firmware;
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typedef struct _psp_directory_header {
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uint32_t cookie;
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uint32_t checksum;
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uint32_t num_entries;
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uint32_t reserved;
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} __attribute__((packed, aligned(16))) psp_directory_header;
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typedef struct _psp_directory_entry {
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uint8_t type;
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uint8_t subprog;
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uint16_t rsvd;
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uint32_t size;
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uint64_t addr; /* or a value in some cases */
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} __attribute__((packed)) psp_directory_entry;
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typedef struct _psp_directory_table {
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psp_directory_header header;
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psp_directory_entry entries[];
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} __attribute__((packed)) psp_directory_table;
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#define MAX_PSP_ENTRIES 0x1f
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typedef struct _psp_combo_header {
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uint32_t cookie;
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uint32_t checksum;
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uint32_t num_entries;
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uint32_t lookup;
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uint64_t reserved[2];
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} __attribute__((packed, aligned(16))) psp_combo_header;
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typedef struct _psp_combo_entry {
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uint32_t id_sel;
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uint32_t id;
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uint64_t lvl2_addr;
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} __attribute__((packed)) psp_combo_entry;
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typedef struct _psp_combo_directory {
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psp_combo_header header;
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psp_combo_entry entries[];
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} __attribute__((packed)) psp_combo_directory;
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#define MAX_COMBO_ENTRIES 1
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typedef struct _context {
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char *rom; /* target buffer, size of flash device */
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uint32_t rom_size; /* size of flash device */
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uint32_t current; /* pointer within flash & proxy buffer */
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} context;
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#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1)
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#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset))
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#define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current)
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#define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))
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#define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current)
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#define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom))
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#define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current)
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static void *new_psp_dir(context *ctx, int multi)
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{
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void *ptr;
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/*
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* Force both onto boundary when multi. Primary table is after
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* updatable table, so alignment ensures primary can stay intact
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* if secondary is reprogrammed.
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*/
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if (multi)
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ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT);
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else
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ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
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ptr = BUFF_CURRENT(*ctx);
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ctx->current += sizeof(psp_directory_header)
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+ MAX_PSP_ENTRIES * sizeof(psp_directory_entry);
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return ptr;
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}
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static void *new_combo_dir(context *ctx)
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{
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void *ptr;
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ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
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ptr = BUFF_CURRENT(*ctx);
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ctx->current += sizeof(psp_combo_header)
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+ MAX_COMBO_ENTRIES * sizeof(psp_combo_entry);
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return ptr;
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}
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static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie)
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{
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psp_combo_directory *cdir = directory;
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psp_directory_table *dir = directory;
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if (!count)
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return;
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switch (cookie) {
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case PSP2_COOKIE:
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/* caller is responsible for lookup mode */
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cdir->header.cookie = cookie;
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cdir->header.num_entries = count;
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cdir->header.reserved[0] = 0;
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cdir->header.reserved[1] = 0;
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/* checksum everything that comes after the Checksum field */
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cdir->header.checksum = fletcher32(&cdir->header.num_entries,
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count * sizeof(psp_combo_entry)
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+ sizeof(cdir->header.num_entries)
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+ sizeof(cdir->header.lookup)
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+ 2 * sizeof(cdir->header.reserved[0]));
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break;
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case PSP_COOKIE:
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case PSPL2_COOKIE:
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dir->header.cookie = cookie;
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dir->header.num_entries = count;
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dir->header.reserved = 0;
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/* checksum everything that comes after the Checksum field */
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dir->header.checksum = fletcher32(&dir->header.num_entries,
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count * sizeof(psp_directory_entry)
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+ sizeof(dir->header.num_entries)
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+ sizeof(dir->header.reserved));
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break;
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}
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}
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static ssize_t copy_blob(void *dest, const char *src_file, size_t room)
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{
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int fd;
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struct stat fd_stat;
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ssize_t bytes;
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fd = open(src_file, O_RDONLY);
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if (fd < 0) {
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printf("Error: %s\n", strerror(errno));
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return -1;
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}
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if (fstat(fd, &fd_stat)) {
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printf("fstat error: %s\n", strerror(errno));
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return -2;
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}
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if (fd_stat.st_size > room) {
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printf("Error: %s will not fit. Exiting.\n", src_file);
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return -3;
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}
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bytes = read(fd, dest, (size_t)fd_stat.st_size);
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close(fd);
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if (bytes != (ssize_t)fd_stat.st_size) {
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printf("Error while reading %s\n", src_file);
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return -4;
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}
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return bytes;
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}
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static void integrate_firmwares(context *ctx,
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embedded_firmware *romsig,
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amd_fw_entry *fw_table)
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{
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ssize_t bytes;
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int i;
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|
|
ctx->current += sizeof(embedded_firmware);
|
|
ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
|
|
|
|
for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
|
|
if (fw_table[i].filename != NULL) {
|
|
switch (fw_table[i].type) {
|
|
case AMD_FW_IMC:
|
|
ctx->current = ALIGN(ctx->current, 0x10000U);
|
|
romsig->imc_entry = RUN_CURRENT(*ctx);
|
|
break;
|
|
case AMD_FW_GEC:
|
|
romsig->gec_entry = RUN_CURRENT(*ctx);
|
|
break;
|
|
case AMD_FW_XHCI:
|
|
romsig->xhci_entry = RUN_CURRENT(*ctx);
|
|
break;
|
|
default:
|
|
/* Error */
|
|
break;
|
|
}
|
|
|
|
bytes = copy_blob(BUFF_CURRENT(*ctx),
|
|
fw_table[i].filename, BUFF_ROOM(*ctx));
|
|
if (bytes < 0) {
|
|
free(ctx->rom);
|
|
exit(1);
|
|
}
|
|
|
|
ctx->current = ALIGN(ctx->current + bytes,
|
|
BLOB_ALIGNMENT);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void integrate_psp_firmwares(context *ctx,
|
|
psp_directory_table *pspdir,
|
|
psp_directory_table *pspdir2,
|
|
amd_fw_entry *fw_table,
|
|
uint32_t cookie)
|
|
{
|
|
ssize_t bytes;
|
|
unsigned int i, count;
|
|
int level;
|
|
|
|
/* This function can create a primary table, a secondary table, or a
|
|
* flattened table which contains all applicable types. These if-else
|
|
* statements infer what the caller intended. If a 2nd-level cookie
|
|
* is passed, clearly a 2nd-level table is intended. However, a
|
|
* 1st-level cookie may indicate level 1 or flattened. If the caller
|
|
* passes a pointer to a 2nd-level table, then assume not flat.
|
|
*/
|
|
if (cookie == PSPL2_COOKIE)
|
|
level = PSP_LVL2;
|
|
else if (pspdir2)
|
|
level = PSP_LVL1;
|
|
else
|
|
level = PSP_BOTH;
|
|
|
|
ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
|
|
|
|
for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
|
|
if (!(fw_table[i].level & level))
|
|
continue;
|
|
|
|
if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) {
|
|
pspdir->entries[count].type = fw_table[i].type;
|
|
pspdir->entries[count].subprog = fw_table[i].subprog;
|
|
pspdir->entries[count].rsvd = 0;
|
|
pspdir->entries[count].size = 0xFFFFFFFF;
|
|
pspdir->entries[count].addr = fw_table[i].other;
|
|
count++;
|
|
} else if (fw_table[i].type == AMD_FW_PSP_NVRAM) {
|
|
if (fw_table[i].filename == NULL)
|
|
continue;
|
|
/* TODO: Add a way to reserve for NVRAM without
|
|
* requiring a filename. This isn't a feature used
|
|
* by coreboot systems, so priority is very low.
|
|
*/
|
|
ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
|
|
bytes = copy_blob(BUFF_CURRENT(*ctx),
|
|
fw_table[i].filename, BUFF_ROOM(*ctx));
|
|
if (bytes <= 0) {
|
|
free(ctx->rom);
|
|
exit(1);
|
|
}
|
|
|
|
pspdir->entries[count].type = fw_table[i].type;
|
|
pspdir->entries[count].subprog = fw_table[i].subprog;
|
|
pspdir->entries[count].rsvd = 0;
|
|
pspdir->entries[count].size = ALIGN(bytes,
|
|
ERASE_ALIGNMENT);
|
|
pspdir->entries[count].addr = RUN_CURRENT(*ctx);
|
|
|
|
ctx->current = ALIGN(ctx->current + bytes,
|
|
BLOB_ERASE_ALIGNMENT);
|
|
count++;
|
|
} else if (fw_table[i].filename != NULL) {
|
|
bytes = copy_blob(BUFF_CURRENT(*ctx),
|
|
fw_table[i].filename, BUFF_ROOM(*ctx));
|
|
if (bytes < 0) {
|
|
free(ctx->rom);
|
|
exit(1);
|
|
}
|
|
|
|
pspdir->entries[count].type = fw_table[i].type;
|
|
pspdir->entries[count].subprog = fw_table[i].subprog;
|
|
pspdir->entries[count].rsvd = 0;
|
|
pspdir->entries[count].size = (uint32_t)bytes;
|
|
pspdir->entries[count].addr = RUN_CURRENT(*ctx);
|
|
|
|
ctx->current = ALIGN(ctx->current + bytes,
|
|
BLOB_ALIGNMENT);
|
|
count++;
|
|
} else {
|
|
/* This APU doesn't have this firmware. */
|
|
}
|
|
}
|
|
|
|
if (pspdir2) {
|
|
pspdir->entries[count].type = AMD_FW_L2_PTR;
|
|
pspdir->entries[count].subprog = 0;
|
|
pspdir->entries[count].rsvd = 0;
|
|
pspdir->entries[count].size = sizeof(pspdir2->header)
|
|
+ pspdir2->header.num_entries
|
|
* sizeof(psp_directory_entry);
|
|
|
|
pspdir->entries[count].addr = BUFF_TO_RUN(*ctx, pspdir2);
|
|
count++;
|
|
}
|
|
|
|
if (count > MAX_PSP_ENTRIES) {
|
|
printf("Error: PSP entries exceed max allowed items\n");
|
|
free(ctx->rom);
|
|
exit(1);
|
|
}
|
|
|
|
fill_dir_header(pspdir, count, cookie);
|
|
}
|
|
|
|
static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:o:f:l:h";
|
|
|
|
static struct option long_options[] = {
|
|
{"xhci", required_argument, 0, 'x' },
|
|
{"imc", required_argument, 0, 'i' },
|
|
{"gec", required_argument, 0, 'g' },
|
|
/* PSP */
|
|
{"combo-capable", no_argument, 0, 'A' },
|
|
{"multilevel", no_argument, 0, 'M' },
|
|
{"subprogram", required_argument, 0, 'S' },
|
|
{"pubkey", required_argument, 0, 'p' },
|
|
{"bootloader", required_argument, 0, 'b' },
|
|
{"smufirmware", required_argument, 0, 's' },
|
|
{"recovery", required_argument, 0, 'r' },
|
|
{"rtmpubkey", required_argument, 0, 'k' },
|
|
{"secureos", required_argument, 0, 'c' },
|
|
{"nvram", required_argument, 0, 'n' },
|
|
{"securedebug", required_argument, 0, 'd' },
|
|
{"trustlets", required_argument, 0, 't' },
|
|
{"trustletkey", required_argument, 0, 'u' },
|
|
{"smufirmware2", required_argument, 0, 'w' },
|
|
{"smuscs", required_argument, 0, 'm' },
|
|
{"soft-fuse", required_argument, 0, 'T' },
|
|
{"output", required_argument, 0, 'o' },
|
|
{"flashsize", required_argument, 0, 'f' },
|
|
{"location", required_argument, 0, 'l' },
|
|
{"help", no_argument, 0, 'h' },
|
|
|
|
{NULL, 0, 0, 0 }
|
|
};
|
|
|
|
static void register_fw_fuse(char *str)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
|
|
if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN)
|
|
continue;
|
|
|
|
amd_psp_fw_table[i].other = strtoull(str, NULL, 16);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[])
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) {
|
|
if (amd_fw_table[i].type == type) {
|
|
amd_fw_table[i].filename = filename;
|
|
return;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
|
|
if (amd_psp_fw_table[i].type != type)
|
|
continue;
|
|
|
|
if (amd_psp_fw_table[i].subprog == sub) {
|
|
amd_psp_fw_table[i].filename = filename;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
int main(int argc, char **argv)
|
|
{
|
|
int c;
|
|
int retval = 0;
|
|
char *tmp;
|
|
char *rom = NULL;
|
|
embedded_firmware *amd_romsig;
|
|
psp_directory_table *pspdir;
|
|
int comboable = 0;
|
|
int fuse_defined = 0;
|
|
int targetfd;
|
|
char *output = NULL;
|
|
context ctx = {
|
|
.rom_size = CONFIG_ROM_SIZE,
|
|
};
|
|
uint32_t dir_location = 0;
|
|
uint32_t romsig_offset;
|
|
uint32_t rom_base_address;
|
|
uint8_t sub = 0;
|
|
int multi = 0;
|
|
|
|
while (1) {
|
|
int optindex = 0;
|
|
|
|
c = getopt_long(argc, argv, optstring, long_options, &optindex);
|
|
|
|
if (c == -1)
|
|
break;
|
|
|
|
switch (c) {
|
|
case 'x':
|
|
register_fw_filename(AMD_FW_XHCI, sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'i':
|
|
register_fw_filename(AMD_FW_IMC, sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'g':
|
|
register_fw_filename(AMD_FW_GEC, sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'A':
|
|
comboable = 1;
|
|
break;
|
|
case 'M':
|
|
multi = 1;
|
|
break;
|
|
case 'S':
|
|
sub = (uint8_t)strtoul(optarg, &tmp, 16);
|
|
break;
|
|
case 'p':
|
|
register_fw_filename(AMD_FW_PSP_PUBKEY, sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'b':
|
|
register_fw_filename(AMD_FW_PSP_BOOTLOADER,
|
|
sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 's':
|
|
register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE,
|
|
sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'r':
|
|
register_fw_filename(AMD_FW_PSP_RECOVERY, sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'k':
|
|
register_fw_filename(AMD_FW_PSP_RTM_PUBKEY,
|
|
sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'c':
|
|
register_fw_filename(AMD_FW_PSP_SECURED_OS,
|
|
sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'n':
|
|
register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'd':
|
|
register_fw_filename(AMD_FW_PSP_SECURED_DEBUG,
|
|
sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 't':
|
|
register_fw_filename(AMD_FW_PSP_TRUSTLETS, sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'u':
|
|
register_fw_filename(AMD_FW_PSP_TRUSTLETKEY,
|
|
sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'w':
|
|
register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2,
|
|
sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'm':
|
|
register_fw_filename(AMD_FW_PSP_SMUSCS, sub, optarg);
|
|
sub = 0;
|
|
break;
|
|
case 'T':
|
|
register_fw_fuse(optarg);
|
|
fuse_defined = 1;
|
|
sub = 0;
|
|
break;
|
|
case 'o':
|
|
output = optarg;
|
|
break;
|
|
case 'f':
|
|
ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16);
|
|
if (*tmp != '\0') {
|
|
printf("Error: ROM size specified"
|
|
" incorrectly (%s)\n\n", optarg);
|
|
retval = 1;
|
|
}
|
|
break;
|
|
case 'l':
|
|
dir_location = (uint32_t)strtoul(optarg, &tmp, 16);
|
|
if (*tmp != '\0') {
|
|
printf("Error: Directory Location specified"
|
|
" incorrectly (%s)\n\n", optarg);
|
|
retval = 1;
|
|
}
|
|
break;
|
|
|
|
case 'h':
|
|
usage();
|
|
return 0;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!fuse_defined)
|
|
register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN);
|
|
|
|
if (!output) {
|
|
printf("Error: Output value is not specified.\n\n");
|
|
retval = 1;
|
|
}
|
|
|
|
if (ctx.rom_size % 1024 != 0) {
|
|
printf("Error: ROM Size (%d bytes) should be a multiple of"
|
|
" 1024 bytes.\n\n", ctx.rom_size);
|
|
retval = 1;
|
|
}
|
|
|
|
if (ctx.rom_size < MIN_ROM_KB * 1024) {
|
|
printf("Error: ROM Size (%dKB) must be at least %dKB.\n\n",
|
|
ctx.rom_size / 1024, MIN_ROM_KB);
|
|
retval = 1;
|
|
}
|
|
|
|
if (retval) {
|
|
usage();
|
|
return retval;
|
|
}
|
|
|
|
printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024);
|
|
|
|
rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1;
|
|
if (dir_location && (dir_location < rom_base_address)) {
|
|
printf("Error: Directory location outside of ROM.\n\n");
|
|
return 1;
|
|
}
|
|
|
|
switch (dir_location) {
|
|
case 0: /* Fall through */
|
|
case 0xFFFA0000: /* Fall through */
|
|
case 0xFFF20000: /* Fall through */
|
|
case 0xFFE20000: /* Fall through */
|
|
case 0xFFC20000: /* Fall through */
|
|
case 0xFF820000: /* Fall through */
|
|
case 0xFF020000: /* Fall through */
|
|
break;
|
|
default:
|
|
printf("Error: Invalid Directory location.\n");
|
|
printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n");
|
|
printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n");
|
|
return 1;
|
|
}
|
|
|
|
ctx.rom = malloc(ctx.rom_size);
|
|
if (!ctx.rom) {
|
|
printf("Error: Failed to allocate memory\n");
|
|
return 1;
|
|
}
|
|
memset(ctx.rom, 0xFF, ctx.rom_size);
|
|
|
|
if (dir_location)
|
|
romsig_offset = ctx.current = dir_location - rom_base_address;
|
|
else
|
|
romsig_offset = ctx.current = AMD_ROMSIG_OFFSET;
|
|
printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n",
|
|
RUN_CURRENT(ctx));
|
|
|
|
amd_romsig = BUFF_OFFSET(ctx, romsig_offset);
|
|
amd_romsig->signature = EMBEDDED_FW_SIGNATURE;
|
|
amd_romsig->imc_entry = 0;
|
|
amd_romsig->gec_entry = 0;
|
|
amd_romsig->xhci_entry = 0;
|
|
|
|
integrate_firmwares(&ctx, amd_romsig, amd_fw_table);
|
|
|
|
ctx.current = ALIGN(ctx.current, 0x10000U); /* todo: is necessary? */
|
|
|
|
if (multi) {
|
|
/* Do 2nd PSP directory followed by 1st */
|
|
psp_directory_table *pspdir2 = new_psp_dir(&ctx, multi);
|
|
integrate_psp_firmwares(&ctx, pspdir2, 0,
|
|
amd_psp_fw_table, PSPL2_COOKIE);
|
|
|
|
pspdir = new_psp_dir(&ctx, multi);
|
|
integrate_psp_firmwares(&ctx, pspdir, pspdir2,
|
|
amd_psp_fw_table, PSP_COOKIE);
|
|
} else {
|
|
/* flat: PSP 1 cookie and no pointer to 2nd table */
|
|
pspdir = new_psp_dir(&ctx, multi);
|
|
integrate_psp_firmwares(&ctx, pspdir, 0,
|
|
amd_psp_fw_table, PSP_COOKIE);
|
|
}
|
|
|
|
if (comboable)
|
|
amd_romsig->comboable = BUFF_TO_RUN(ctx, pspdir);
|
|
else
|
|
amd_romsig->psp_entry = BUFF_TO_RUN(ctx, pspdir);
|
|
|
|
#if PSP_COMBO
|
|
psp_combo_directory *combo_dir = new_combo_dir(&ctx);
|
|
amd_romsig->comboable = BUFF_TO_RUN(ctx, combo_dir);
|
|
/* 0 -Compare PSP ID, 1 -Compare chip family ID */
|
|
combo_dir->entries[0].id_sel = 0;
|
|
/* TODO: PSP ID. Documentation is needed. */
|
|
combo_dir->entries[0].id = 0x10220B00;
|
|
combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir);
|
|
|
|
combo_dir->header.lookup = 1;
|
|
fill_dir_header(combo_dir, 1, PSP2_COOKIE);
|
|
#endif
|
|
|
|
targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666);
|
|
if (targetfd >= 0) {
|
|
write(targetfd, amd_romsig, ctx.current - romsig_offset);
|
|
close(targetfd);
|
|
} else {
|
|
printf("Error: could not open file: %s\n", output);
|
|
retval = 1;
|
|
}
|
|
|
|
free(rom);
|
|
return retval;
|
|
}
|