3511b92d31
For all other CPUs, we unconditionally include the CPU Kconfig files in the CPU directory, not in the vendor directory. Do the same thing for the Exynos CPUs. This allows us to make CPU dependent changes in the directory of that CPU alone. Also, drop some unused Kconfig variables from the Exynos Kconfig files. Change-Id: I4e4c22a0693988834e619dd33d121bf994ed57e8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3683 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
136 lines
2.7 KiB
Text
136 lines
2.7 KiB
Text
config CPU_SAMSUNG_EXYNOS5250
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depends on ARCH_ARMV7
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select HAVE_MONOTONIC_TIMER
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select HAVE_UART_SPECIAL
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select DEFAULT_BOOTBLOCK_CONSOLE
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select DEFAULT_EARLY_CONSOLE
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bool
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default n
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if CPU_SAMSUNG_EXYNOS5250
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config BOOTBLOCK_CPU_INIT
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string
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default "cpu/samsung/exynos5250/bootblock.c"
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help
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CPU/SoC-specific bootblock code. This is useful if the
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bootblock must load microcode or copy data from ROM before
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searching for the bootblock.
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# ROM image layout.
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#
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# 0x0000: vendor-provided BL1 (8k).
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# 0x2000: bootblock
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# 0x2010-0x2090: reserved for CBFS master header.
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# 0xA000: Free for CBFS data.
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config BOOTBLOCK_ROM_OFFSET
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hex
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default 0x2000
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x2010
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config CBFS_ROM_OFFSET
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# Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
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hex "offset of CBFS data in ROM"
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default 0x0A000
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# Example SRAM/iRAM map for Exynos5250 platform:
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#
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# 0x0202_0000: vendor-provided BL1
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# 0x0202_3400: bootblock, assume up to 32KB in size
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# 0x0203_0000: romstage, assume up to 128KB in size.
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# 0x0207_8000: stack pointer
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config BOOTBLOCK_BASE
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hex
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default 0x02023400
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config ROMSTAGE_BASE
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hex
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default 0x02030000
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config ROMSTAGE_SIZE
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hex
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default 0x10000
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# Stack may reside in either IRAM or DRAM. We will define it to live
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# at the top of IRAM for now.
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#
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# Stack grows downward, push operation stores register contents in
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# consecutive memory locations ending just below SP
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config STACK_TOP
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hex
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default 0x02078000
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config STACK_BOTTOM
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hex
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default 0x02077000
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config STACK_SIZE
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hex
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default 0x1000
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# TODO We may probably move this to board-specific implementation files instead
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# of KConfig values.
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config CBFS_CACHE_ADDRESS
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hex "memory address to put CBFS cache data"
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default 0x02060000
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config CBFS_CACHE_SIZE
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hex "size of CBFS cache data"
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default 0x000017000
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config SYS_SDRAM_BASE
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hex
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default 0x40000000
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config SYS_TEXT_BASE
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hex
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default 0x43e00000
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config COREBOOT_TABLES_SIZE
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hex
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default 0x4000000
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choice CONSOLE_SERIAL_UART_CHOICES
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prompt "Serial Console UART"
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default CONSOLE_SERIAL_UART3
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depends on CONSOLE_SERIAL_UART
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config CONSOLE_SERIAL_UART0
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bool "UART0"
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help
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Serial console on UART0
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config CONSOLE_SERIAL_UART1
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bool "UART1"
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help
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Serial console on UART1
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config CONSOLE_SERIAL_UART2
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bool "UART2"
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help
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Serial console on UART2
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config CONSOLE_SERIAL_UART3
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bool "UART3"
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help
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Serial console on UART3
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endchoice
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config CONSOLE_SERIAL_UART_ADDRESS
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hex
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depends on CONSOLE_SERIAL_UART
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default 0x12c00000 if CONSOLE_SERIAL_UART0
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default 0x12c10000 if CONSOLE_SERIAL_UART1
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default 0x12c20000 if CONSOLE_SERIAL_UART2
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default 0x12c30000 if CONSOLE_SERIAL_UART3
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help
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Map the UART names to the respective MMIO address.
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endif
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