Felix Held b93a9a282f soc/amd/common/block/gpio_banks/gpio: add comment in check_gpios ... Each bit in the GPIO wake status index registers is set to 1 when at least one of 4 corresponding GPIO pins has its wake status register set. Added the comment since the gpio_base + i * 4 in the next line looked as if it calculates some absolute register value which is not what the code does or should be doing. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-07-31 01:28:39 +00:00
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cezanne	soc/amd/*/chip.h: Correct PSPP Enum Value	2021-07-24 19:49:45 +00:00
common	soc/amd/common/block/gpio_banks/gpio: add comment in check_gpios	2021-07-31 01:28:39 +00:00
picasso	soc/amd/*/chip.h: Correct PSPP Enum Value	2021-07-24 19:49:45 +00:00
stoneyridge	soc/amd/common/block/acpimmio: add Kconfig option for biosram accessors	2021-07-26 19:34:20 +00:00
Kconfig