b9590799b3
- The hotplug register doesn't work in the way we describe. Just leave it at default. - The backlight registers will be configured by the OS driver. BUG=chrome-os-partner:27304 TEST=Manual on Rambi. Boot system in both dev and normal mode, verify that display comes up. Also verify that display functions after warm reboot and suspend / resume. BRANCH=rambi+squawks Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193830 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3f287cc31e41fabef755c37361e2e65ca413c88c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
372 lines
13 KiB
C
372 lines
13 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <reg_script.h>
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#include <baytrail/gfx.h>
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#include <baytrail/iosf.h>
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#include <baytrail/pci_devs.h>
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#include <baytrail/ramstage.h>
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#include "chip.h"
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#define GFX_TIMEOUT 100000 /* 100ms */
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/*
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* Lock Power Context Base Register to point to a 24KB block
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* of memory in GSM. Power context save data is stored here.
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*/
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static void gfx_lock_pcbase(device_t dev)
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{
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,
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288,320,352,384,416,448,480,512 };
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u32 pcsize = 24 << 10; /* 24KB */
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u32 wopcmsz = 0x100000; /* PAVP offset */
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u32 gms, gmsize, pcbase;
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gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK;
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gms >>= 3;
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if (gms > sizeof(gms_size_map))
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return;
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gmsize = gms_size_map[gms];
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/* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */
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pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000;
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pcbase += (gmsize-1) * wopcmsz - pcsize;
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pcbase |= 1; /* Lock */
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write32(res->base + 0x182120, pcbase);
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}
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static const struct reg_script gfx_init_script[] = {
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/* Allow-Wake render/media wells */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT),
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/* Render Force-Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000,
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GFX_TIMEOUT),
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/* Media Force-Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000,
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GFX_TIMEOUT),
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/* Workaround - X0:261954/A0:261955 */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1),
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/*
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* PowerMeter Weights
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*/
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/* SET1 */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000),
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/* SET2 */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000),
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/* SET3 */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000),
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/* Enable PowerMeter Counters */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058),
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/* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */
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/* SDP Profile 4 == 0x11940, others 0xcf08 */
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REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08),
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/* GfxPause */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388),
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/* Dynamic EU Control Settings */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004),
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/* Lock ECO Bit Settings */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000),
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/* DOP Clock Gating */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001),
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/* MBCunit will send the VCR (Fuse) writes as NP-W */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000),
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/*
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* RC6 Settings
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*/
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000),
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/* RC1e - RC6/6p - RC6pp Wake Rate Limits */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019),
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/* RC Sleep / RCx Thresholds */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557),
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/*
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* Turbo Settings
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*/
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/* Render/Video/Blitter Idle Max Count */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A),
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/* RP Down Timeout */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240),
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/*
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* Turbo Control Settings
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*/
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/* RP Up/Down Threshold */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08),
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/* RP Up/Down EI */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730),
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/* RP Idle Hysteresis */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a),
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/* HW RC6 Control Settings */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000),
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/* RP Control */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592),
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/* Enable PM Interrupts */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e),
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/* Aggressive Clock Gating */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0),
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/* Enable Gfx Turbo. */
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REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG,
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~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0),
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REG_SCRIPT_END
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};
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static const struct reg_script gpu_pre_vbios_script[] = {
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/* Make sure GFX is bus master with MMIO access */
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REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
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/* Display */
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REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
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REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0,
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GFX_TIMEOUT),
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/* Tx/Rx Lanes */
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REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0),
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REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0,
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GFX_TIMEOUT),
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/* Common Lane */
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REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0),
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REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0,
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GFX_TIMEOUT),
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/* Ungating Tx only */
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REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0),
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REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0,
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GFX_TIMEOUT),
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/* Ungating Common Lane only */
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REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0),
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REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0,
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GFX_TIMEOUT),
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/* Ungating Display */
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REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000),
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REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000,
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GFX_TIMEOUT),
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REG_SCRIPT_END
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};
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static const struct reg_script gfx_post_vbios_script[] = {
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/* Deassert Render Force-Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT),
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/* Deassert Media Force-Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT),
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/* Set Lock bits */
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REG_PCI_RMW32(GGC, 0xffffffff, 1),
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REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1),
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REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1),
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REG_SCRIPT_END
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};
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static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
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{
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reg_script_run_on_dev(dev, ops);
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}
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static void gfx_pre_vbios_init(device_t dev)
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{
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printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
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gfx_run_script(dev, gpu_pre_vbios_script);
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}
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static void gfx_pm_init(device_t dev)
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{
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printk(BIOS_INFO, "GFX: Power Management Init\n");
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gfx_run_script(dev, gfx_init_script);
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/* Lock power context base */
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gfx_lock_pcbase(dev);
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}
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static void gfx_post_vbios_init(device_t dev)
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{
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printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
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gfx_run_script(dev, gfx_post_vbios_script);
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}
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static void gfx_panel_setup(device_t dev)
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{
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struct soc_intel_baytrail_config *config = dev->chip_info;
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struct reg_script gfx_pipea_init[] = {
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/* CONTROL */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL),
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PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
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/* POWER ON */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS),
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(config->gpu_pipea_port_select << 30 |
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config->gpu_pipea_power_on_delay << 16 |
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config->gpu_pipea_light_on_delay)),
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/* POWER OFF */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS),
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(config->gpu_pipea_power_off_delay << 16 |
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config->gpu_pipea_light_off_delay)),
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/* DIVISOR */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR),
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~0x1f, config->gpu_pipea_power_cycle_delay),
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REG_SCRIPT_END
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};
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struct reg_script gfx_pipeb_init[] = {
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/* CONTROL */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL),
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PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
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/* POWER ON */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS),
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(config->gpu_pipeb_port_select << 30 |
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config->gpu_pipeb_power_on_delay << 16 |
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config->gpu_pipeb_light_on_delay)),
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/* POWER OFF */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS),
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(config->gpu_pipeb_power_off_delay << 16 |
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config->gpu_pipeb_light_off_delay)),
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/* DIVISOR */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR),
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~0x1f, config->gpu_pipeb_power_cycle_delay),
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REG_SCRIPT_END
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};
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if (config->gpu_pipea_port_select) {
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printk(BIOS_INFO, "GFX: Initialize PIPEA\n");
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reg_script_run_on_dev(dev, gfx_pipea_init);
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}
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if (config->gpu_pipeb_port_select) {
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printk(BIOS_INFO, "GFX: Initialize PIPEB\n");
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reg_script_run_on_dev(dev, gfx_pipeb_init);
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}
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}
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static void gfx_init(device_t dev)
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{
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/* Pre VBIOS Init */
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gfx_pre_vbios_init(dev);
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/* Power Management Init */
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gfx_pm_init(dev);
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gfx_panel_setup(dev);
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/* Run VBIOS */
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pci_dev_init(dev);
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/* Post VBIOS Init */
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gfx_post_vbios_init(dev);
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}
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static struct device_operations gfx_device_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
|
|
.init = gfx_init,
|
|
.ops_pci = &soc_pci_ops,
|
|
};
|
|
|
|
static const struct pci_driver gfx_driver __pci_driver = {
|
|
.ops = &gfx_device_ops,
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = GFX_DEVID,
|
|
};
|