coreboot-kgpe-d16/src/mainboard/google/snow
David Hendricks b959fbb87a exynos5: Re-factor I2C code
This re-factors the Exynos5 I2C code to be simpler and use the
new API, and updates users accordingly.

- i2c_read() and i2c_write() functions updated to take bus number
  as an argument.

- Get rid of the EEPROM_ADDR_OVERFLOW stuff in i2c_read() and
  i2c_write(). If a chip needs special handling we should take care
  of it elsewhere, not in every low-level i2c driver.

- All the confusing bus config functions eliminated. No more
  i2c_set_early_config() or i2c_set_bus() or i2c_get_bus(). All this
  is handled automatically when the caller does a transaction and
  specifies the desired bus number.

- i2c_probe() eliminated. We're not a command-line utility.

- Let the compiler place static variables automatically. We don't need
  any of this fancy manual data placement.

- Remove dead code while we're at it. This stuff was ported early on
  and much of it was left commented out in case we needed it. Some
  also includes nested macros which caused gcc to complain.

- Clean up #includes (no more common.h, woohoo!), replace debug() with
  printk().

Change-Id: I8e1f974ea4c6c7db9f33b77bbc4fb16008ed0d2a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3044
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 00:01:02 +02:00
..
bootblock.c exynos5: Re-factor I2C code 2013-04-10 00:01:02 +02:00
chromeos.c Unify coreboot table generation 2013-03-22 00:17:55 +01:00
devicetree.cb exynos5-common: get rid of displayport trial code 2013-04-05 20:17:35 +02:00
Kconfig samsung/exynos5: add display port and framebuffer defines and initialization 2013-03-06 23:41:42 +01:00
mainboard.c Chromebooks: mainboard.c: Do not spell Chromebook in CamelCase 2013-02-14 19:25:54 +01:00
mainboard.h exynos/snow: Move core/memory clock-related and board ID code 2013-02-06 02:11:14 +01:00
Makefile.inc Drop SRC_ROOT from mainboard Makefile.incs 2013-02-28 17:59:44 +01:00
memory.c exynos/snow: Move core/memory clock-related and board ID code 2013-02-06 02:11:14 +01:00
ramstage.c snow: explicitly configure L2 cache 2013-03-29 22:24:35 +01:00
romstage.c exynos5: Re-factor I2C code 2013-04-10 00:01:02 +02:00