4e8baf9202
The XTAL shutdown (dis)qualification bit already unconditionally gets set to 1 by FSP for these platforms, making this code redundant. Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
98 lines
2.2 KiB
C
98 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor PCH Datasheet
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* Document number: 621483
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* Chapter number: 4, 29
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*/
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include <device/pci.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/thermal.h>
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#include <spi-generic.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
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#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
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#define CAM_CLK_EN (1 << 1)
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#define MIPI_CLK (1 << 0)
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#define HDPLL_CLK (0 << 0)
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static void pch_enable_isclk(void)
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{
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pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
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pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
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}
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static void pch_handle_sideband(config_t *config)
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{
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if (config->pch_isclk)
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pch_enable_isclk();
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}
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static void pch_finalize(void)
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{
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config_t *config;
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/* TCO Lock down */
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tco_lockdown();
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/* TODO: Add Thermal Configuration */
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/*
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* Disable ACPI PM timer based on dt policy
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*/
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config = config_of_soc();
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if (config->PmTimerDisabled)
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pmc_disable_acpi_timer();
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pch_handle_sideband(config);
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pmc_clear_pmcon_sts();
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}
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static void tbt_finalize(void)
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{
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int i;
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const struct device *dev;
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/* Disable Thunderbolt PCIe root ports bus master */
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for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
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dev = pcidev_path_on_root(SA_DEVFN_TBT(i));
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if (dev)
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pci_dev_disable_bus_master(dev);
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}
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}
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static void soc_finalize(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize();
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apm_control(APM_CNT_FINALIZE);
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tbt_finalize();
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
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