9fe20cb381
Samsung SoC files, including Exynos5 (a Cortex-A15
implementation). Since this is an SoC we'll forego the x86-style
{north,south}bridge and cpu distinction. We may try to split some
stuff out before the final version if prudent.
Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2005
Tested-by: build bot (Jenkins)
90 lines
2 KiB
C
90 lines
2 KiB
C
/*
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* Copyright (c) 2012 Samsung Electronics.
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* Arun Mankuzhi <arun.m@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <system.h>
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#include <armv7.h>
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enum l2_cache_params {
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CACHE_TAG_RAM_SETUP = (1<<9),
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CACHE_DATA_RAM_SETUP = (1<<5),
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CACHE_TAG_RAM_LATENCY = (2<<6),
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CACHE_DATA_RAM_LATENCY = (2<<0)
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};
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/* FIXME(dhendrix): maybe move this to a romstage-specific file? */
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#ifdef __PRE_RAM__
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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/*
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* Set L2 cache parameters
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*/
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static void exynos5_set_l2cache_params(void)
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{
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unsigned int val = 0;
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asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
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val |= CACHE_TAG_RAM_SETUP |
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CACHE_DATA_RAM_SETUP |
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CACHE_TAG_RAM_LATENCY |
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CACHE_DATA_RAM_LATENCY;
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asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
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}
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/*
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* Sets L2 cache related parameters before enabling data cache
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*/
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void v7_outer_cache_enable(void)
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{
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exynos5_set_l2cache_params();
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}
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/* stubs so we don't need weak symbols in cache_v7.c */
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void v7_outer_cache_disable(void)
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{
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}
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void v7_outer_cache_flush_all(void)
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{
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}
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void v7_outer_cache_inval_all(void)
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{
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}
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void v7_outer_cache_flush_range(u32 start, u32 end)
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{
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}
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void v7_outer_cache_inval_range(u32 start, u32 end)
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{
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}
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