9fe20cb381
Samsung SoC files, including Exynos5 (a Cortex-A15
implementation). Since this is an SoC we'll forego the x86-style
{north,south}bridge and cpu distinction. We may try to split some
stuff out before the final version if prudent.
Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2005
Tested-by: build bot (Jenkins)
47 lines
1.3 KiB
C
47 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cpu/samsung/exynos5250/cpu.h>
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#include <cpu/samsung/exynos5250/periph.h>
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#include <cpu/samsung/exynos5250/uart.h>
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enum periph_id exynos5_get_periph_id(unsigned base_addr)
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{
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enum periph_id id = PERIPH_ID_NONE;
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switch (base_addr) {
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case EXYNOS5_UART0_BASE:
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id = PERIPH_ID_UART0;
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break;
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case EXYNOS5_UART1_BASE:
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id = PERIPH_ID_UART1;
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break;
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case EXYNOS5_UART2_BASE:
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id = PERIPH_ID_UART2;
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break;
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case EXYNOS5_UART3_BASE:
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id = PERIPH_ID_UART3;
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break;
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default:
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break;
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}
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return id;
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}
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