ba295dce84
and expose the error earlier in the build. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
158 lines
4.2 KiB
C
158 lines
4.2 KiB
C
#ifndef EARLYMTRR_C
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#define EARLYMTRR_C
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
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#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
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# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
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#endif
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#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
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# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
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#endif
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#if !defined(CONFIG_RAMTOP)
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# error "CONFIG_RAMTOP not defined"
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#endif
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#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
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# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
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#endif
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#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
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# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
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#endif
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#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
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# error "CONFIG_RAMTOP must be a power of 2"
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#endif
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static void disable_var_mtrr(unsigned reg)
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{
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/* The invalid bit is kept in the mask so we simply
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* clear the relevent mask register to disable a
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* range.
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*/
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msr_t zero;
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zero.lo = zero.hi = 0;
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wrmsr(MTRRphysMask_MSR(reg), zero);
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}
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static void set_var_mtrr(
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unsigned reg, unsigned base, unsigned size, unsigned type)
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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/* FIXME: It only support 4G less range */
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msr_t basem, maskm;
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basem.lo = base | type;
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basem.hi = 0;
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wrmsr(MTRRphysBase_MSR(reg), basem);
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maskm.lo = ~(size - 1) | 0x800;
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maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
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wrmsr(MTRRphysMask_MSR(reg), maskm);
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}
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static void set_var_mtrr_x(
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unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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msr_t basem, maskm;
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basem.lo = (base_lo & 0xfffff000) | type;
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basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1);
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wrmsr(MTRRphysBase_MSR(reg), basem);
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maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
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if(size_lo) {
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maskm.lo = ~(size_lo - 1) | 0x800;
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} else {
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maskm.lo = 0x800;
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maskm.hi &= ~(size_hi - 1);
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}
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wrmsr(MTRRphysMask_MSR(reg), maskm);
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}
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static void cache_lbmem(int type)
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{
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/* Enable caching for 0 - 1MB using variable mtrr */
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disable_cache();
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set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type);
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enable_cache();
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}
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/* the fixed and variable MTTRs are power-up with random values,
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* clear them to MTRR_TYPE_UNCACHEABLE for safty.
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*/
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static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
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{
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/* Precondition:
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* The cache is not enabled in cr0 nor in MTRRdefType_MSR
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* entry32.inc ensures the cache is not enabled in cr0
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*/
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msr_t msr;
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const unsigned long *msr_addr;
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/* Inialize all of the relevant msrs to 0 */
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msr.lo = 0;
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msr.hi = 0;
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unsigned long msr_nr;
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for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
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wrmsr(msr_nr, msr);
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}
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#if defined(CONFIG_XIP_ROM_SIZE)
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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extern unsigned long AUTO_XIP_ROM_BASE;
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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#else
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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/* enable write through caching so we can do execute in place
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* on the flash rom.
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*/
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set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
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#endif
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/* Set the default memory type and enable fixed and variable MTRRs
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*/
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/* Enable Variable MTRRs */
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msr.hi = 0x00000000;
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msr.lo = 0x00000800;
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wrmsr(MTRRdefType_MSR, msr);
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}
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static void early_mtrr_init(void)
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{
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static const unsigned long mtrr_msrs[] = {
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/* fixed mtrr */
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0x250, 0x258, 0x259,
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0x268, 0x269, 0x26A,
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0x26B, 0x26C, 0x26D,
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0x26E, 0x26F,
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/* var mtrr */
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0x200, 0x201, 0x202, 0x203,
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0x204, 0x205, 0x206, 0x207,
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0x208, 0x209, 0x20A, 0x20B,
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0x20C, 0x20D, 0x20E, 0x20F,
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/* NULL end of table */
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0
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};
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disable_cache();
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do_early_mtrr_init(mtrr_msrs);
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enable_cache();
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}
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static int early_mtrr_init_detected(void)
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{
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msr_t msr;
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/* See if MTRR's are enabled.
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* a #RESET disables them while an #INIT
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* preserves their state. This works
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* on both Intel and AMD cpus, at least
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* according to the documentation.
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*/
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msr = rdmsr(MTRRdefType_MSR);
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return msr.lo & 0x00000800;
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}
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#endif /* EARLYMTRR_C */
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