Kane Chen ba9b7bfc6f baytrail: add code for supporting 2x ddr refresh rate ... this code change provides a way to enable 2x refresh rate in RW image In baytrail, it enables 2x refresh rate by default BUG=chrome-os-partner:35210 BRANCH=none TEST=check the register is set properly on rambi Change-Id: I2a935b570c564986898b6c2064fc7ad43506dcba Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c740d403708862514be9fa24f56b2764328979eb Original-Change-Id: I84f33d75ea7ebfea180b304e8ff683884f0dbe8a Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241754 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9498 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2015-04-10 20:18:19 +02:00
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imgtec	pistachio: add timer frequency for SOC; correct platform ID	2015-04-09 02:32:59 +02:00
intel	baytrail: add code for supporting 2x ddr refresh rate	2015-04-10 20:18:19 +02:00
marvell	vboot: move vboot files to designated directory	2015-04-10 16:46:55 +02:00
nvidia	vboot: move vboot files to designated directory	2015-04-10 16:46:55 +02:00
qualcomm	ipq806x: Remove extra INCLUDES	2015-04-10 12:02:49 +02:00
rockchip	vboot: move vboot files to designated directory	2015-04-10 16:46:55 +02:00
samsung	gpio: Extend common GPIO header, simplify function names	2015-04-10 11:57:33 +02:00
ucb	kconfig: drop intermittend forwarder files	2015-04-07 17:40:28 +02:00
Makefile.inc	cosmos: add template for soc and board files	2015-04-09 00:21:21 +02:00