coreboot-kgpe-d16/src
Paul Menzel bae3f06245 AMD CIMx SB800: Update Kconfig help texts to new SATA mode default
In the following commit

    commit ee5c111755
    Author: Paul Menzel <paulepanter@users.sourceforge.net>
    Date:   Tue Mar 12 12:41:40 2013 +0100

        AMD CIMx SB800: Enable AHCI mode for SATA controller by default

        Reviewed-on: http://review.coreboot.org/2661

I forgot to update the help texts to the new SATA mode default. Do
so now.

Additionally note that help texts for `choice` do not seem to be
shown.

Change-Id: I17f401633a2136efca2b21a621482e0724ff9f04
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2936
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29 21:33:38 +01:00
..
arch armv7: update sync barrier usage in dcache_op_set_way() 2013-03-29 21:12:54 +01:00
console dynamic cbmem: fix memconsole and timestamps 2013-03-23 19:44:25 +01:00
cpu x86: mtrr: optimize hole carving above 4GiB 2013-03-29 20:12:20 +01:00
device ramstage: prepare for relocation 2013-03-21 18:01:38 +01:00
drivers x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
ec x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
include memrange: add 2 new range_entry routines 2013-03-29 20:11:28 +01:00
lib memrange: add 2 new range_entry routines 2013-03-29 20:11:28 +01:00
mainboard wtm2: auto-select CACHE_ROM 2013-03-29 21:11:27 +01:00
northbridge sandybridge: add option to mark graphics memory write-combining. 2013-03-29 20:00:39 +01:00
southbridge AMD CIMx SB800: Update Kconfig help texts to new SATA mode default 2013-03-29 21:33:38 +01:00
superio x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
vendorcode chromeos: remove CACHE_ROM automatic selection 2013-03-29 20:10:57 +01:00
Kconfig dynamic cbmem: fix memconsole and timestamps 2013-03-23 19:44:25 +01:00