029aaf627c
The access to control registers were scattered about.
Provide a single header file to provide the correct
access function and definitions.
BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted using this infrastructure. Also objdump'd the
assembly to ensure consistency (objdump -d -r -S | grep xmm).
Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172641
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4873
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
113 lines
2.4 KiB
C
113 lines
2.4 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CPU_X86_CR_H
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#define CPU_X86_CR_H
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#if !defined(__ASSEMBLER__)
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#include <stdint.h>
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#include <arch/cpu.h>
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/* ROMCC apparently chokes certain clobber registers. */
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#if defined(__ROMCC__)
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#define COMPILER_BARRIER
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#else
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#define COMPILER_BARRIER "memory"
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#endif
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static alwaysinline uint32_t read_cr0(void)
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{
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uint32_t value;
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__asm__ __volatile__ (
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"mov %%cr0, %0"
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: "=r" (value)
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:
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: COMPILER_BARRIER
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);
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return value;
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}
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static alwaysinline void write_cr0(uint32_t data)
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{
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__asm__ __volatile__ (
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"mov %0, %%cr0"
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:
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: "r" (data)
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: COMPILER_BARRIER
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);
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}
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static alwaysinline uint32_t read_cr4(void)
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{
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uint32_t value;
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__asm__ __volatile__ (
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"mov %%cr4, %0"
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: "=r" (value)
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:
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: COMPILER_BARRIER
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);
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return value;
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}
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static alwaysinline void write_cr4(uint32_t data)
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{
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__asm__ __volatile__ (
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"mov %0, %%cr4"
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:
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: "r" (data)
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: COMPILER_BARRIER
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);
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}
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#endif /* !defined(__ASSEMBLER__) */
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/* CR0 flags */
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#define CR0_PE (1 << 0)
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#define CR0_MP (1 << 1)
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#define CR0_EM (1 << 2)
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#define CR0_TS (1 << 3)
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#define CR0_ET (1 << 4)
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#define CR0_NE (1 << 5)
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#define CR0_WP (1 << 16)
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#define CR0_AM (1 << 18)
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#define CR0_NW (1 << 29)
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#define CR0_CD (1 << 30)
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#define CR0_PG (1 << 31)
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/* CR4 flags */
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#define CR4_VME (1 << 0)
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#define CR4_PVI (1 << 1)
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#define CR4_TSD (1 << 2)
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#define CR4_DE (1 << 3)
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#define CR4_PSE (1 << 4)
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#define CR4_PAE (1 << 5)
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#define CR4_MCE (1 << 6)
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#define CR4_PGE (1 << 7)
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#define CR4_PCE (1 << 8)
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#define CR4_OSFXSR (1 << 9)
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#define CR4_OSXMMEXCPT (1 << 10)
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#define CR4_VMXE (1 << 13)
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#define CR4_SMXE (1 << 14)
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#define CR4_FSGSBASE (1 << 16)
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#define CR4_PCIDE (1 << 17)
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#define CR4_OSXSAVE (1 << 18)
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#define CR4_SMEP (1 << 20)
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#endif /* CPU_X86_CR_H */
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