312fc96874
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM registers on ICH5. Add ICH5 and i865 to the supported chips list. Enable the dumping of BAR6 on i865. Sample output: Disabling memory access: $ sudo setpci -s 6.0 0x04.b=0x0 $ sudo ./inteltool -m | head -n 9 Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7 Intel Northbridge: 8086:2570 (i865) Intel Southbridge: 8086:24d0 (ICH5) ============= MCHBAR ============ Access to BAR6 is currently disabled, attempting to enable. Enabled successfully. BAR6 = 0xfecf0000 (MEM) Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Joseph Smith <joe@settoplinux.org> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
80 lines
2.3 KiB
C
80 lines
2.3 KiB
C
/*
|
|
* inteltool - dump all registers on an Intel CPU + chipset based system.
|
|
*
|
|
* Copyright (C) 2008 by coresystems GmbH
|
|
* written by Stefan Reinauer <stepan@coresystems.de>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
*/
|
|
|
|
#include <stdio.h>
|
|
#include <stdlib.h>
|
|
#include "inteltool.h"
|
|
|
|
int print_rcba(struct pci_dev *sb)
|
|
{
|
|
int i, size = 0x4000;
|
|
volatile uint8_t *rcba;
|
|
uint32_t rcba_phys;
|
|
|
|
printf("\n============= RCBA ==============\n\n");
|
|
|
|
switch (sb->device_id) {
|
|
case PCI_DEVICE_ID_INTEL_ICH6:
|
|
case PCI_DEVICE_ID_INTEL_ICH7:
|
|
case PCI_DEVICE_ID_INTEL_ICH7M:
|
|
case PCI_DEVICE_ID_INTEL_ICH7DH:
|
|
case PCI_DEVICE_ID_INTEL_ICH7MDH:
|
|
case PCI_DEVICE_ID_INTEL_ICH8:
|
|
case PCI_DEVICE_ID_INTEL_ICH8M:
|
|
case PCI_DEVICE_ID_INTEL_ICH9DH:
|
|
case PCI_DEVICE_ID_INTEL_ICH9DO:
|
|
case PCI_DEVICE_ID_INTEL_ICH9R:
|
|
case PCI_DEVICE_ID_INTEL_ICH9:
|
|
case PCI_DEVICE_ID_INTEL_ICH9M:
|
|
case PCI_DEVICE_ID_INTEL_ICH9ME:
|
|
case PCI_DEVICE_ID_INTEL_ICH10R:
|
|
case PCI_DEVICE_ID_INTEL_NM10:
|
|
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
|
|
break;
|
|
case PCI_DEVICE_ID_INTEL_ICH:
|
|
case PCI_DEVICE_ID_INTEL_ICH0:
|
|
case PCI_DEVICE_ID_INTEL_ICH2:
|
|
case PCI_DEVICE_ID_INTEL_ICH4:
|
|
case PCI_DEVICE_ID_INTEL_ICH4M:
|
|
case PCI_DEVICE_ID_INTEL_ICH5:
|
|
printf("This southbridge does not have RCBA.\n");
|
|
return 1;
|
|
default:
|
|
printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
|
|
return 1;
|
|
}
|
|
|
|
rcba = map_physical(rcba_phys, size);
|
|
|
|
if (rcba == NULL) {
|
|
perror("Error mapping RCBA");
|
|
exit(1);
|
|
}
|
|
|
|
printf("RCBA = 0x%08x (MEM)\n\n", rcba_phys);
|
|
|
|
for (i = 0; i < size; i += 4) {
|
|
if (*(uint32_t *)(rcba + i))
|
|
printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i));
|
|
}
|
|
|
|
unmap_physical((void *)rcba, size);
|
|
return 0;
|
|
}
|