897 lines
19 KiB
Go
897 lines
19 KiB
Go
/* This is just an experiment. Full automatic porting
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is probably not possible but a lot can be automated. */
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package main
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import (
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"bytes"
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"flag"
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"fmt"
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"log"
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"os"
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"sort"
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"strings"
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)
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type PCIAddr struct {
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Bus int
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Dev int
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Func int
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}
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type PCIDevData struct {
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PCIAddr
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PCIVenID uint16
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PCIDevID uint16
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ConfigDump []uint8
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}
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type PCIDevice interface {
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Scan(ctx Context, addr PCIDevData)
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}
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type InteltoolData struct {
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GPIO map[uint16]uint32
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RCBA map[uint16]uint32
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IGD map[uint32]uint32
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}
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type DMIData struct {
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Vendor string
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Model string
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Version string
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IsLaptop bool
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}
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type AzaliaCodec struct {
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Name string
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VendorID uint32
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SubsystemID uint32
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CodecNo int
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PinConfig map[int]uint32
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}
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type DevReader interface {
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GetPCIList() []PCIDevData
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GetDMI() DMIData
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GetInteltool() InteltoolData
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GetAzaliaCodecs() []AzaliaCodec
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GetACPI() map[string][]byte
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GetCPUModel() []uint32
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GetEC() []byte
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GetIOPorts() []IOPorts
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HasPS2() bool
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}
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type IOPorts struct {
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Start uint16
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End uint16
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Usage string
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}
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type SouthBridger interface {
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GetGPIOHeader() string
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EncodeGPE(int) int
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DecodeGPE(int) int
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EnableGPE(int)
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NeedRouteGPIOManually()
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}
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var SouthBridge SouthBridger
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var BootBlockFiles map[string]string = map[string]string{}
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var ROMStageFiles map[string]string = map[string]string{}
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var RAMStageFiles map[string]string = map[string]string{}
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var SMMFiles map[string]string = map[string]string{}
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var MainboardInit string
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var MainboardEnable string
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var MainboardIncludes []string
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type Context struct {
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MoboID string
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KconfigName string
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Vendor string
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Model string
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BaseDirectory string
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InfoSource DevReader
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SaneVendor string
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}
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type IOAPICIRQ struct {
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APICID int
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IRQNO [4]int
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}
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var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{}
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var KconfigBool map[string]bool = map[string]bool{}
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var KconfigComment map[string]string = map[string]string{}
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var KconfigString map[string]string = map[string]string{}
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var KconfigHex map[string]uint32 = map[string]uint32{}
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var KconfigInt map[string]int = map[string]int{}
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var ROMSizeKB = 0
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var ROMProtocol = ""
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var FlashROMSupport = ""
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func GetLE16(inp []byte) uint16 {
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return uint16(inp[0]) | (uint16(inp[1]) << 8)
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}
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func FormatHexLE16(inp []byte) string {
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return fmt.Sprintf("0x%04x", GetLE16(inp))
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}
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func FormatHex32(u uint32) string {
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return fmt.Sprintf("0x%08x", u)
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}
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func FormatHex8(u uint8) string {
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return fmt.Sprintf("0x%02x", u)
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}
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func FormatInt32(u uint32) string {
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return fmt.Sprintf("%d", u)
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}
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func FormatHexLE32(d []uint8) string {
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u := uint32(d[0]) | (uint32(d[1]) << 8) | (uint32(d[2]) << 16) | (uint32(d[3]) << 24)
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return FormatHex32(u)
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}
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func FormatBool(inp bool) string {
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if inp {
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return "1"
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} else {
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return "0"
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}
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}
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func sanitize(inp string) string {
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result := strings.ToLower(inp)
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result = strings.Replace(result, " ", "_", -1)
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result = strings.Replace(result, ",", "_", -1)
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result = strings.Replace(result, "-", "_", -1)
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for strings.HasSuffix(result, ".") {
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result = result[0 : len(result)-1]
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}
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return result
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}
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func AddBootBlockFile(Name string, Condition string) {
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BootBlockFiles[Name] = Condition
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}
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func AddROMStageFile(Name string, Condition string) {
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ROMStageFiles[Name] = Condition
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}
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func AddRAMStageFile(Name string, Condition string) {
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RAMStageFiles[Name] = Condition
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}
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func AddSMMFile(Name string, Condition string) {
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SMMFiles[Name] = Condition
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}
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func IsIOPortUsedBy(ctx Context, port uint16, name string) bool {
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for _, io := range ctx.InfoSource.GetIOPorts() {
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if io.Start <= port && port <= io.End && io.Usage == name {
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return true
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}
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}
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return false
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}
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var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory")
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func writeMF(mf *os.File, files map[string]string, category string) {
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keys := []string{}
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for file, _ := range files {
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keys = append(keys, file)
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}
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sort.Strings(keys)
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for _, file := range keys {
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condition := files[file]
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if condition == "" {
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fmt.Fprintf(mf, "%s-y += %s\n", category, file)
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} else {
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fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, condition, file)
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}
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}
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}
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func Create(ctx Context, name string) *os.File {
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li := strings.LastIndex(name, "/")
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if li > 0 {
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os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700)
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}
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mf, err := os.Create(ctx.BaseDirectory + "/" + name)
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if err != nil {
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log.Fatal(err)
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}
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return mf
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}
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func Add_gpl(f *os.File) {
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fmt.Fprintln(f, "/* SPDX-License-Identifier: GPL-2.0-only */")
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fmt.Fprintln(f)
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}
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func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) {
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fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n",
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pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
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pcidev.ConfigDump[addr+1],
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pcidev.ConfigDump[addr])
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}
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func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) {
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fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
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pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
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pcidev.ConfigDump[addr+3],
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pcidev.ConfigDump[addr+2],
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pcidev.ConfigDump[addr+1],
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pcidev.ConfigDump[addr])
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}
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func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) {
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fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr])
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}
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type PCISlot struct {
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PCIAddr
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additionalComment string
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writeEmpty bool
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}
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type DevTreeNode struct {
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Bus int
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Dev int
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Func int
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Disabled bool
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Registers map[string]string
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IOs map[uint16]uint16
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Children []DevTreeNode
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PCISlots []PCISlot
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PCIController bool
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ChildPCIBus int
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MissingParent string
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SubVendor uint16
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SubSystem uint16
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Chip string
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Comment string
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}
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var DevTree DevTreeNode
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var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{}
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var unmatchedPCIChips map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{}
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var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{}
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func Offset(dt *os.File, offset int) {
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for i := 0; i < offset; i++ {
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fmt.Fprintf(dt, "\t")
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}
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}
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func MatchDev(dev *DevTreeNode) {
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for idx := range dev.Children {
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MatchDev(&dev.Children[idx])
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}
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for _, slot := range dev.PCISlots {
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slotChip, ok := unmatchedPCIChips[slot.PCIAddr]
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if !ok {
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continue
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}
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if slot.additionalComment != "" && slotChip.Comment != "" {
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slotChip.Comment = slot.additionalComment + " " + slotChip.Comment
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} else {
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slotChip.Comment = slot.additionalComment + slotChip.Comment
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}
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delete(unmatchedPCIChips, slot.PCIAddr)
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MatchDev(&slotChip)
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dev.Children = append(dev.Children, slotChip)
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}
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if dev.PCIController {
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for slot, slotDev := range unmatchedPCIChips {
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if slot.Bus == dev.ChildPCIBus {
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delete(unmatchedPCIChips, slot)
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MatchDev(&slotDev)
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dev.Children = append(dev.Children, slotDev)
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}
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}
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}
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for _, slot := range dev.PCISlots {
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slotDev, ok := unmatchedPCIDevices[slot.PCIAddr]
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if !ok {
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if slot.writeEmpty {
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dev.Children = append(dev.Children,
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DevTreeNode{
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Registers: map[string]string{},
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Chip: "pci",
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Bus: slot.Bus,
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Dev: slot.Dev,
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Func: slot.Func,
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Comment: slot.additionalComment,
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Disabled: true,
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},
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)
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}
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continue
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}
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if slot.additionalComment != "" && slotDev.Comment != "" {
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slotDev.Comment = slot.additionalComment + " " + slotDev.Comment
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} else {
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slotDev.Comment = slot.additionalComment + slotDev.Comment
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}
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MatchDev(&slotDev)
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dev.Children = append(dev.Children, slotDev)
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delete(unmatchedPCIDevices, slot.PCIAddr)
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}
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if dev.MissingParent != "" {
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for _, child := range MissingChildren[dev.MissingParent] {
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MatchDev(&child)
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dev.Children = append(dev.Children, child)
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}
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delete(MissingChildren, dev.MissingParent)
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}
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if dev.PCIController {
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for slot, slotDev := range unmatchedPCIDevices {
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if slot.Bus == dev.ChildPCIBus {
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MatchDev(&slotDev)
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dev.Children = append(dev.Children, slotDev)
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delete(unmatchedPCIDevices, slot)
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}
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}
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}
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}
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func writeOn(dt *os.File, dev DevTreeNode) {
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if dev.Disabled {
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fmt.Fprintf(dt, "off")
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} else {
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fmt.Fprintf(dt, "on")
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}
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}
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func WriteDev(dt *os.File, offset int, dev DevTreeNode) {
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Offset(dt, offset)
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switch dev.Chip {
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case "cpu_cluster", "lapic", "domain", "ioapic":
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fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev)
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writeOn(dt, dev)
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case "pci", "pnp":
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fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func)
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writeOn(dt, dev)
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case "i2c":
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fmt.Fprintf(dt, "device %s %02x ", dev.Chip, dev.Dev)
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writeOn(dt, dev)
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default:
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fmt.Fprintf(dt, "chip %s", dev.Chip)
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}
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if dev.Comment != "" {
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fmt.Fprintf(dt, " # %s", dev.Comment)
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}
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fmt.Fprintf(dt, "\n")
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if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 {
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Offset(dt, offset+1)
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fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem)
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}
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ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}]
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if dev.Chip == "pci" && ok {
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for pin, irq := range ioapic.IRQNO {
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if irq != 0 {
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Offset(dt, offset+1)
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fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq)
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}
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}
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}
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keys := []string{}
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for reg, _ := range dev.Registers {
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keys = append(keys, reg)
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}
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sort.Strings(keys)
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for _, reg := range keys {
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val := dev.Registers[reg]
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Offset(dt, offset+1)
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fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val)
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}
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ios := []int{}
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for reg, _ := range dev.IOs {
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ios = append(ios, int(reg))
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}
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sort.Ints(ios)
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for _, reg := range ios {
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val := dev.IOs[uint16(reg)]
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Offset(dt, offset+1)
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fmt.Fprintf(dt, "io 0x%x = 0x%x\n", reg, val)
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}
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for _, child := range dev.Children {
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WriteDev(dt, offset+1, child)
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}
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Offset(dt, offset)
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fmt.Fprintf(dt, "end\n")
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}
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func PutChip(domain string, cur DevTreeNode) {
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MissingChildren[domain] = append(MissingChildren[domain], cur)
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}
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func PutPCIChip(addr PCIDevData, cur DevTreeNode) {
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unmatchedPCIChips[addr.PCIAddr] = cur
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}
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func PutPCIDevParent(addr PCIDevData, comment string, parent string) {
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cur := DevTreeNode{
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Registers: map[string]string{},
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Chip: "pci",
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Bus: addr.Bus,
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Dev: addr.Dev,
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Func: addr.Func,
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MissingParent: parent,
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Comment: comment,
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}
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if addr.ConfigDump[0xa] == 0x04 && addr.ConfigDump[0xb] == 0x06 {
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cur.PCIController = true
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cur.ChildPCIBus = int(addr.ConfigDump[0x19])
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loopCtr := 0
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for capPtr := addr.ConfigDump[0x34]; capPtr != 0; capPtr = addr.ConfigDump[capPtr+1] {
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/* Avoid hangs. There are only 0x100 different possible values for capPtr.
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If we iterate longer than that, we're in endless loop. */
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loopCtr++
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if loopCtr > 0x100 {
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break
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}
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if addr.ConfigDump[capPtr] == 0x0d {
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cur.SubVendor = GetLE16(addr.ConfigDump[capPtr+4 : capPtr+6])
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cur.SubSystem = GetLE16(addr.ConfigDump[capPtr+6 : capPtr+8])
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}
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}
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} else {
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cur.SubVendor = GetLE16(addr.ConfigDump[0x2c:0x2e])
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cur.SubSystem = GetLE16(addr.ConfigDump[0x2e:0x30])
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}
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unmatchedPCIDevices[addr.PCIAddr] = cur
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}
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func PutPCIDev(addr PCIDevData, comment string) {
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PutPCIDevParent(addr, comment, "")
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}
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type GenericPCI struct {
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Comment string
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Bus0Subdiv string
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MissingParent string
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}
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type GenericVGA struct {
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GenericPCI
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}
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type DSDTInclude struct {
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Comment string
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File string
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}
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type DSDTDefine struct {
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Key string
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Comment string
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Value string
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}
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var DSDTIncludes []DSDTInclude
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var DSDTPCI0Includes []DSDTInclude
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var DSDTDefines []DSDTDefine
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func (g GenericPCI) Scan(ctx Context, addr PCIDevData) {
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PutPCIDevParent(addr, g.Comment, g.MissingParent)
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}
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var IGDEnabled bool = false
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func (g GenericVGA) Scan(ctx Context, addr PCIDevData) {
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KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x,%04x",
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addr.PCIVenID,
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addr.PCIDevID)
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KconfigString["VGA_BIOS_FILE"] = fmt.Sprintf("pci%04x,%04x.rom",
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addr.PCIVenID,
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addr.PCIDevID)
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PutPCIDevParent(addr, g.Comment, g.MissingParent)
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IGDEnabled = true
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}
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func makeKconfigName(ctx Context) {
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kn := Create(ctx, "Kconfig.name")
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defer kn.Close()
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fmt.Fprintf(kn, "config %s\n\tbool \"%s\"\n", ctx.KconfigName, ctx.Model)
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}
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func makeComment(name string) string {
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cmt, ok := KconfigComment[name]
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if !ok {
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return ""
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}
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return " # " + cmt
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}
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|
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func makeKconfig(ctx Context) {
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kc := Create(ctx, "Kconfig")
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defer kc.Close()
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fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName)
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fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS\n\tdef_bool y\n")
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keys := []string{}
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for name, val := range KconfigBool {
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if val {
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keys = append(keys, name)
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}
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}
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|
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sort.Strings(keys)
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|
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for _, name := range keys {
|
|
fmt.Fprintf(kc, "\tselect %s%s\n", name, makeComment(name))
|
|
}
|
|
|
|
keys = nil
|
|
for name, val := range KconfigBool {
|
|
if !val {
|
|
keys = append(keys, name)
|
|
}
|
|
}
|
|
|
|
sort.Strings(keys)
|
|
|
|
for _, name := range keys {
|
|
fmt.Fprintf(kc, `
|
|
config %s%s
|
|
bool
|
|
default n
|
|
`, name, makeComment(name))
|
|
}
|
|
|
|
keys = nil
|
|
for name, _ := range KconfigString {
|
|
keys = append(keys, name)
|
|
}
|
|
|
|
sort.Strings(keys)
|
|
|
|
for _, name := range keys {
|
|
fmt.Fprintf(kc, `
|
|
config %s%s
|
|
string
|
|
default "%s"
|
|
`, name, makeComment(name), KconfigString[name])
|
|
}
|
|
|
|
keys = nil
|
|
for name, _ := range KconfigHex {
|
|
keys = append(keys, name)
|
|
}
|
|
|
|
sort.Strings(keys)
|
|
|
|
for _, name := range keys {
|
|
fmt.Fprintf(kc, `
|
|
config %s%s
|
|
hex
|
|
default 0x%x
|
|
`, name, makeComment(name), KconfigHex[name])
|
|
}
|
|
|
|
keys = nil
|
|
for name, _ := range KconfigInt {
|
|
keys = append(keys, name)
|
|
}
|
|
|
|
sort.Strings(keys)
|
|
|
|
for _, name := range keys {
|
|
fmt.Fprintf(kc, `
|
|
config %s%s
|
|
int
|
|
default %d
|
|
`, name, makeComment(name), KconfigInt[name])
|
|
}
|
|
|
|
fmt.Fprintf(kc, "endif\n")
|
|
}
|
|
|
|
const MoboDir = "/src/mainboard/"
|
|
|
|
func makeVendor(ctx Context) {
|
|
vendor := ctx.Vendor
|
|
vendorSane := ctx.SaneVendor
|
|
vendorDir := *FlagOutDir + MoboDir + vendorSane
|
|
vendorUpper := strings.ToUpper(vendorSane)
|
|
kconfig := vendorDir + "/Kconfig"
|
|
if _, err := os.Stat(kconfig); os.IsNotExist(err) {
|
|
f, err := os.Create(kconfig)
|
|
if err != nil {
|
|
log.Fatal(err)
|
|
}
|
|
defer f.Close()
|
|
f.WriteString(`if VENDOR_` + vendorUpper + `
|
|
|
|
choice
|
|
prompt "Mainboard model"
|
|
|
|
source "src/mainboard/` + vendorSane + `/*/Kconfig.name"
|
|
|
|
endchoice
|
|
|
|
source "src/mainboard/` + vendorSane + `/*/Kconfig"
|
|
|
|
config MAINBOARD_VENDOR
|
|
string
|
|
default "` + vendor + `"
|
|
|
|
endif # VENDOR_` + vendorUpper + "\n")
|
|
}
|
|
kconfigName := vendorDir + "/Kconfig.name"
|
|
if _, err := os.Stat(kconfigName); os.IsNotExist(err) {
|
|
f, err := os.Create(kconfigName)
|
|
if err != nil {
|
|
log.Fatal(err)
|
|
}
|
|
defer f.Close()
|
|
f.WriteString(`config VENDOR_` + vendorUpper + `
|
|
bool "` + vendor + `"
|
|
`)
|
|
}
|
|
|
|
}
|
|
|
|
func GuessECGPE(ctx Context) int {
|
|
/* FIXME:XX Use iasl -d and/or better parsing */
|
|
dsdt := ctx.InfoSource.GetACPI()["DSDT"]
|
|
idx := bytes.Index(dsdt, []byte{0x08, '_', 'G', 'P', 'E', 0x0a}) /* Name (_GPE, byte). */
|
|
if idx > 0 {
|
|
return int(dsdt[idx+6])
|
|
}
|
|
return -1
|
|
}
|
|
|
|
func GuessSPDMap(ctx Context) []uint8 {
|
|
dmi := ctx.InfoSource.GetDMI()
|
|
|
|
if dmi.Vendor == "LENOVO" {
|
|
return []uint8{0x50, 0x52, 0x51, 0x53}
|
|
}
|
|
return []uint8{0x50, 0x51, 0x52, 0x53}
|
|
}
|
|
|
|
func main() {
|
|
flag.Parse()
|
|
|
|
ctx := Context{}
|
|
|
|
ctx.InfoSource = MakeLogReader()
|
|
|
|
dmi := ctx.InfoSource.GetDMI()
|
|
|
|
ctx.Vendor = dmi.Vendor
|
|
|
|
if dmi.Vendor == "LENOVO" {
|
|
ctx.Model = dmi.Version
|
|
} else {
|
|
ctx.Model = dmi.Model
|
|
}
|
|
|
|
if dmi.IsLaptop {
|
|
KconfigBool["SYSTEM_TYPE_LAPTOP"] = true
|
|
}
|
|
ctx.SaneVendor = sanitize(ctx.Vendor)
|
|
for {
|
|
last := ctx.SaneVendor
|
|
for _, suf := range []string{"_inc", "_co", "_corp"} {
|
|
ctx.SaneVendor = strings.TrimSuffix(ctx.SaneVendor, suf)
|
|
}
|
|
if last == ctx.SaneVendor {
|
|
break
|
|
}
|
|
}
|
|
ctx.MoboID = ctx.SaneVendor + "/" + sanitize(ctx.Model)
|
|
ctx.KconfigName = "BOARD_" + strings.ToUpper(ctx.SaneVendor+"_"+sanitize(ctx.Model))
|
|
ctx.BaseDirectory = *FlagOutDir + MoboDir + ctx.MoboID
|
|
KconfigString["MAINBOARD_DIR"] = ctx.MoboID
|
|
KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model
|
|
|
|
os.MkdirAll(ctx.BaseDirectory, 0700)
|
|
|
|
makeVendor(ctx)
|
|
|
|
ScanRoot(ctx)
|
|
|
|
if IGDEnabled {
|
|
KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true
|
|
KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this"
|
|
AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT")
|
|
}
|
|
|
|
if len(BootBlockFiles) > 0 || len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 {
|
|
mf := Create(ctx, "Makefile.inc")
|
|
defer mf.Close()
|
|
writeMF(mf, BootBlockFiles, "bootblock")
|
|
writeMF(mf, ROMStageFiles, "romstage")
|
|
writeMF(mf, RAMStageFiles, "ramstage")
|
|
writeMF(mf, SMMFiles, "smm")
|
|
}
|
|
|
|
devtree := Create(ctx, "devicetree.cb")
|
|
defer devtree.Close()
|
|
|
|
MatchDev(&DevTree)
|
|
WriteDev(devtree, 0, DevTree)
|
|
|
|
if MainboardInit != "" || MainboardEnable != "" || MainboardIncludes != nil {
|
|
mainboard := Create(ctx, "mainboard.c")
|
|
defer mainboard.Close()
|
|
mainboard.WriteString("#include <device/device.h>\n")
|
|
for _, include := range MainboardIncludes {
|
|
mainboard.WriteString("#include <" + include + ">\n")
|
|
}
|
|
mainboard.WriteString("\n")
|
|
if MainboardInit != "" {
|
|
mainboard.WriteString(`static void mainboard_init(struct device *dev)
|
|
{
|
|
` + MainboardInit + "}\n\n")
|
|
}
|
|
if MainboardInit != "" || MainboardEnable != "" {
|
|
mainboard.WriteString("static void mainboard_enable(struct device *dev)\n{\n")
|
|
if MainboardInit != "" {
|
|
mainboard.WriteString("\tdev->ops->init = mainboard_init;\n\n")
|
|
}
|
|
mainboard.WriteString(MainboardEnable)
|
|
mainboard.WriteString("}\n\n")
|
|
mainboard.WriteString(`struct chip_operations mainboard_ops = {
|
|
.enable_dev = mainboard_enable,
|
|
};
|
|
`)
|
|
}
|
|
}
|
|
|
|
bi := Create(ctx, "board_info.txt")
|
|
defer bi.Close()
|
|
|
|
fixme := ""
|
|
|
|
if dmi.IsLaptop {
|
|
bi.WriteString("Category: laptop\n")
|
|
} else {
|
|
bi.WriteString("Category: desktop\n")
|
|
fixme += "check category, "
|
|
}
|
|
|
|
missing := "ROM package, ROM socketed"
|
|
|
|
if ROMProtocol != "" {
|
|
fmt.Fprintf(bi, "ROM protocol: %s\n", ROMProtocol)
|
|
} else {
|
|
missing += ", ROM protocol"
|
|
}
|
|
|
|
if FlashROMSupport != "" {
|
|
fmt.Fprintf(bi, "Flashrom support: %s\n", FlashROMSupport)
|
|
} else {
|
|
missing += ", Flashrom support"
|
|
}
|
|
|
|
missing += ", Release year"
|
|
|
|
if fixme != "" {
|
|
fmt.Fprintf(bi, "FIXME: %s, put %s\n", fixme, missing)
|
|
} else {
|
|
fmt.Fprintf(bi, "FIXME: put %s\n", missing)
|
|
}
|
|
|
|
if ROMSizeKB == 0 {
|
|
KconfigBool["BOARD_ROMSIZE_KB_2048"] = true
|
|
KconfigComment["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this"
|
|
} else {
|
|
KconfigBool[fmt.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB)] = true
|
|
}
|
|
|
|
makeKconfig(ctx)
|
|
makeKconfigName(ctx)
|
|
|
|
dsdt := Create(ctx, "dsdt.asl")
|
|
defer dsdt.Close()
|
|
|
|
for _, define := range DSDTDefines {
|
|
if define.Comment != "" {
|
|
fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment)
|
|
}
|
|
dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n")
|
|
}
|
|
|
|
dsdt.WriteString(
|
|
`
|
|
|
|
#include <acpi/acpi.h>
|
|
|
|
DefinitionBlock(
|
|
"dsdt.aml",
|
|
"DSDT",
|
|
ACPI_DSDT_REV_2,
|
|
OEM_ID,
|
|
ACPI_TABLE_CREATOR,
|
|
0x20141018 /* OEM revision */
|
|
)
|
|
{
|
|
#include "acpi/platform.asl"
|
|
`)
|
|
|
|
for _, x := range DSDTIncludes {
|
|
if x.Comment != "" {
|
|
fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment)
|
|
}
|
|
fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File)
|
|
}
|
|
|
|
dsdt.WriteString(`
|
|
Device (\_SB.PCI0)
|
|
{
|
|
`)
|
|
for _, x := range DSDTPCI0Includes {
|
|
if x.Comment != "" {
|
|
fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment)
|
|
}
|
|
fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File)
|
|
}
|
|
dsdt.WriteString(
|
|
` }
|
|
}
|
|
`)
|
|
|
|
if IGDEnabled {
|
|
gma := Create(ctx, "gma-mainboard.ads")
|
|
defer gma.Close()
|
|
|
|
gma.WriteString(`-- SPDX-License-Identifier: GPL-2.0-or-later
|
|
|
|
with HW.GFX.GMA;
|
|
with HW.GFX.GMA.Display_Probing;
|
|
|
|
use HW.GFX.GMA;
|
|
use HW.GFX.GMA.Display_Probing;
|
|
|
|
private package GMA.Mainboard is
|
|
|
|
-- FIXME: check this
|
|
ports : constant Port_List :=
|
|
(DP1,
|
|
DP2,
|
|
DP3,
|
|
HDMI1,
|
|
HDMI2,
|
|
HDMI3,
|
|
Analog,
|
|
LVDS,
|
|
eDP);
|
|
|
|
end GMA.Mainboard;
|
|
`)
|
|
}
|
|
}
|