1c6d8a9cf4
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* This file is created based on Intel Tiger Lake Processor SA Datasheet
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* Document number: 571131
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* Chapter number: 4
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*/
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#include <arch/acpi.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <drivers/intel/gma/opregion.h>
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#include <intelblocks/graphics.h>
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#include <types.h>
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uintptr_t fsp_soc_get_igd_bar(void)
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{
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return graphics_get_memory_base();
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}
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void graphics_soc_init(struct device *dev)
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{
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uint32_t ddi_buf_ctl;
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/* Skip IGD GT programming */
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if (CONFIG(SKIP_GRAPHICS_ENABLING))
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return;
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/*
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* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
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* This will allow the kernel to use 4-lane eDP links properly
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* if the VBIOS or GOP driver do not execute.
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*/
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ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
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if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
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ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED |
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DDI_BUF_IS_IDLE);
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graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
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}
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/*
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* GFX PEIM module inside FSP binary is taking care of graphics
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* initialization based on RUN_FSP_GOP Kconfig
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* option and input VBT file. Hence no need to load/execute legacy VGA
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* OpROM in order to initialize GFX.
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*
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* In case of non-FSP solution, SoC need to select VGA_ROM_RUN
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* Kconfig to perform GFX initialization through VGA OpRom.
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*/
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if (CONFIG(RUN_FSP_GOP))
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return;
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/* IGD needs to Bus Master */
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uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Initialize PCI device, load/execute BIOS Option ROM */
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pci_dev_init(dev);
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}
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uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
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uintptr_t current, struct acpi_rsdp *rsdp)
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{
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igd_opregion_t *opregion;
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printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
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opregion = (igd_opregion_t *)current;
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if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
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return current;
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current += sizeof(igd_opregion_t);
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return acpi_align_current(current);
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}
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