a46a712610
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
161 lines
5.4 KiB
C
161 lines
5.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
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*
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* Copyright (C) 2006 AMD
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* Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
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*
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* Copyright (C) 2006 MSI
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* Written by bxshi <bingxunshi@gmail.com> for MSI.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <arch/io.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#if CONFIG_LOGICAL_CPUS
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#include <cpu/amd/multicore.h>
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#endif
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#include <cpu/amd/amdk8_sysconf.h>
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#include "mb_sysconf.h"
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int i, bus_isa;
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struct mb_sysconf_t *m;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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get_bus_conf();
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m = sysconf.mb;
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mptable_write_buses(mc, NULL, &bus_isa);
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/*I/O APICs: APIC ID Version State Address*/
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{
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device_t dev = 0;
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struct resource *res;
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for(i=0; i<3; i++) {
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dev = dev_find_device(0x1166, 0x0235, dev);
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
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}
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}
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}
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}
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mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
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//IDE
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outb(0x02, 0xc00); outb(0x0e, 0xc01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE
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//SATA
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outb(0x07, 0xc00); outb(0x0f, 0xc01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf);
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//USB
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outb(0x01, 0xc00); outb(0x0a, 0xc01);
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for(i=0;i<3;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
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}
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/* enable int */
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/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
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{
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device_t dev;
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dev = dev_find_device(0x1166, 0x0205, 0);
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if(dev) {
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uint32_t dword;
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dword = pci_read_config32(dev, 0x6c);
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dword |= (1<<4); // enable interrupts
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pci_write_config32(dev, 0x6c, dword);
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}
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}
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//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
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// AIC 8130 Galileo Technology...
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
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}
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//pci slot (on bcm5785)
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); //
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}
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//onboard ati
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);
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//PCI-X on bcm5780
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
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}
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//onboard Broadcom
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for(i=0;i<2;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
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}
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// First PCI-E x8
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); //
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}
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// Second PCI-E x8
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); //
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}
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// Third PCI-E x1
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); //
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}
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
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mptable_lintsrc(mc, bus_isa);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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