c6f6be0929
Including raminit Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4044 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
43 lines
1.3 KiB
Makefile
43 lines
1.3 KiB
Makefile
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2010 Google Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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ramstage-y += northbridge.c
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ramstage-y += gma.c
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ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
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ramstage-y += ../sandybridge/mrccache.c
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romstage-y += raminit.c
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romstage-y += early_init.c
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romstage-y += ../sandybridge/mrccache.c
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romstage-y += ../../../arch/x86/lib/walkcbfs.S
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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$(obj)/mrc.cache:
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dd if=/dev/zero count=1 \
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bs=$(shell printf "%d" $(CONFIG_TRAINING_CACHE_SIZE) ) | \
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tr '\000' '\377' > $@
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cbfs-files-y += mrc.cache
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mrc.cache-file := $(obj)/mrc.cache
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mrc.cache-position := 0xfff80000
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mrc.cache-type := 0xac
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$(obj)/northbridge/intel/nehalem/acpi.ramstage.o : $(obj)/build.h
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