100 lines
3.5 KiB
C
100 lines
3.5 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdint.h>
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#if defined(__GLIBC__)
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#include <sys/io.h>
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#endif
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#if (defined(__MACH__) && defined(__APPLE__))
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/* DirectIO is available here: http://www.coresystems.de/en/directio */
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#define __DARWIN__
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#include <DirectIO/darwinio.h>
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#endif
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#include <pci/pci.h>
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#define INTELTOOL_VERSION "1.0"
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/* Tested chipsets: */
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
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#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
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#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
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#define PCI_DEVICE_ID_INTEL_ICH6 0x2640
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#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
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#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
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#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
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#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
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#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
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#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912
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#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914
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#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916
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#define PCI_DEVICE_ID_INTEL_ICH9 0x2918
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#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919
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#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
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#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82830M 0x3575
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#define PCI_DEVICE_ID_INTEL_82845 0x1a30
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#define PCI_DEVICE_ID_INTEL_82915 0x2580
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#define PCI_DEVICE_ID_INTEL_82945P 0x2770
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
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#define PCI_DEVICE_ID_INTEL_82975X 0x277c
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#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
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#define PCI_DEVICE_ID_INTEL_82G33 0x29c0
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#define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
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#define PCI_DEVICE_ID_INTEL_GS45 0x2a40
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#define PCI_DEVICE_ID_INTEL_X58 0x3405
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
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#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
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/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
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#define PCI_DEVICE_ID_INTEL_82443BX 0x7190
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#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
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/* 82371AB/EB/MB use the same device ID value. */
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#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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#ifndef __DARWIN__
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typedef struct { uint32_t hi, lo; } msr_t;
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#endif
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typedef struct { uint16_t addr; int size; char *name; } io_register_t;
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void *map_physical(unsigned long phys_addr, size_t len);
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void unmap_physical(void *virt_addr, size_t len);
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unsigned int cpuid(unsigned int op);
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int print_intel_core_msrs(void);
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int print_mchbar(struct pci_dev *nb);
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int print_pmbase(struct pci_dev *sb);
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int print_rcba(struct pci_dev *sb);
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int print_gpios(struct pci_dev *sb);
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int print_epbar(struct pci_dev *nb);
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int print_dmibar(struct pci_dev *nb);
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int print_pciexbar(struct pci_dev *nb);
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