90d00dea55
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
55 lines
1.3 KiB
Text
55 lines
1.3 KiB
Text
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <variant/ec.h>
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#include <variant/gpio.h>
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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/* global NVS and variables */
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#include <soc/intel/apollolake/acpi/globalnvs.asl>
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/* CPU */
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/apollolake/acpi/northbridge.asl>
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#include <soc/intel/apollolake/acpi/southbridge.asl>
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#include <soc/intel/apollolake/acpi/pch_hda.asl>
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}
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}
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include <variant/acpi/dptf.asl>
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/* Include soc specific DPTF changes */
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#include <soc/intel/apollolake/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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}
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}
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