coreboot-kgpe-d16/payloads/libpayload/arch
Ionela Voinescu 66fc77d3af libpayload: mips: add memcmp to the MIPS string functions
The default string functions work with multiple of 4 bytes
(sizeof(unsinged long)); MIPS will use LW/SW instructions
for these operations and if the source and destination
addresses are not aligned it will trigger an exception.
Therefore, this implementation does all data access operations
per byte, because there is no guarantee that the provided
strings are properly aligned.

BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; behaves as expected
BRANCH=none

Change-Id: I05b43673deb954f022d12cb9c3d7baac26be2a34
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e13b3d31726404abd8c8e5c8780d3d3e16e032d
Original-Change-Id: I456e312eb6b7fee2eff10e461af7f578aed07648
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241885
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21 11:08:16 +01:00
..
arm libpayload: Consolidate coreboot table parsing 2015-03-20 15:31:59 +01:00
arm64 libpayload arm64: Add function to get coreboot table ptr 2015-03-21 10:34:33 +01:00
mips libpayload: mips: add memcmp to the MIPS string functions 2015-03-21 11:08:16 +01:00
x86 libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplication 2015-03-20 15:33:47 +01:00
Config.in libpayload: arch/mips: Add basic MIPS architecture support 2015-03-21 11:07:50 +01:00