Patrick Georgi be61a17351 Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board ... which uses it. Compiles, but not boot tested lately. Many things missing (eg. SMM support, proper ACPI, ...) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2010-12-18 07:48:43 +00:00
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amd	Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3.	2010-12-13 20:43:33 +00:00
intel	Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board	2010-12-18 07:48:43 +00:00
via	drop one more version of doing serial uart output differently.	2010-12-17 00:08:21 +00:00
Kconfig	Drop remainders of PPC port	2009-10-28 19:40:46 +00:00
Makefile.inc	Drop remainders of PPC port	2009-10-28 19:40:46 +00:00