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James Ye be6fd4c4b5 mb/lenovo: add Lenovo ThinkPad X131e (Intel)
The Intel version of ThinkPad X131e can ship with Sandy Bridge or
Ivy Bridge processors.  The mainboard uses 8MiB+4MiB flash chips, with
the 8MiB chip containing the IFD and ME, and the 4MiB chip containing
the BIOS.  The flash chips can be accessed with an external programmer.

This port was primarily created using autoport, with some parts adapted
from lenovo/x230 and google/stout.

Tested and working:
 - Machine type 3367AH5 / Intel Celeron 887 (Sandy Bridge)
 - Boots Debian GNU/Linux 9.2 (Linux 4.9.51) via SeaBIOS
 - Boot from internal SATA and USB
 - Native RAM init
 - Native VGA init
 - libgfxinit
 - VGA and HDMI display output
 - Keyboard, trackpoint, touchpad
 - Audio (speaker, headphones)
 - Ethernet (Realtek)
 - Display backlight
 - USB 3.0 ports
 - "Always on" USB port (EHCI debug)
 - SD card reader
 - Webcam
 - Fan and temperature sensors
 - ACPI S3 (Sleep)
 - CMOS
 - TPM

Not tested:
 - WLAN/Bluetooth (Broadcom)
 - WWAN/mSATA (no card)
 - Other operating systems

Not working or not implemented:
 - Fn keys
 - ACPI S4 (Hibernation) "Image mismatch: memory size"

Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/20694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20 16:54:08 +00:00
3rdparty drivers/intel/gma: Power up legacy VGA block early 2017-12-12 09:20:07 +00:00
Documentation Documentation/Intel: Add NativeRaminit documentation 2017-12-09 16:59:16 +00:00
configs configs: Add intel/harcuvar FSP 2.0 sample configuration 2017-10-04 02:56:33 +00:00
payloads payloads/SeaBIOS: Add different MMIO uart configurations 2017-12-20 16:39:50 +00:00
src mb/lenovo: add Lenovo ThinkPad X131e (Intel) 2017-12-20 16:54:08 +00:00
util util/inteltool: Add GPU device IDs 2017-12-20 16:41:46 +00:00
.checkpatch.conf .checkpatch.conf: Ignore CORRUPTED_PATCH lint 2017-10-29 10:11:58 +00:00
.clang-format
.gitignore .gitignore: Do not track `util/cbfstool/cbfs-compression-tool` 2017-11-03 15:20:40 +00:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview
COPYING update license template. 2006-08-12 22:03:36 +00:00
MAINTAINERS MAINTAINERS: add maintainers for all PC Engines mainboards 2017-10-31 15:45:53 +00:00
Makefile build system: Deal with wildcard in subdirs-y 2017-10-29 08:48:54 +00:00
Makefile.inc util/gitconfig: Make gitconfig a bash script 2017-12-15 23:02:11 +00:00
README README: Update requirements 2017-06-27 17:04:32 +00:00
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
toolchain.inc toolchain: Always use GCC for Ada sources 2017-09-23 10:57:40 +00:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * https://www.coreboot.org/Supported_Motherboards
 * https://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)
 * pkg-config
 * libssl-dev (openssl)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult https://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  https://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.