Yidi Lin be8621d785 soc/mediatek/mt8195: Disable UFS reference clock ... UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage. Change UFSHCI base register to 0x11270000. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>		2021-05-11 03:54:09 +00:00
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common	soc/mediatek/mt8195: Add RTC driver	2021-05-10 01:58:28 +00:00
mt8173	soc/mediatek: Move the power domain data under each SoC	2021-05-05 07:37:21 +00:00
mt8183	soc/mediatek: Move the power domain data under each SoC	2021-05-05 07:37:21 +00:00
mt8192	soc/mediatek/mt8195: Add RTC driver	2021-05-10 01:58:28 +00:00
mt8195	soc/mediatek/mt8195: Disable UFS reference clock	2021-05-11 03:54:09 +00:00
Kconfig