be929f41af
On kevin board, both the gpio2ab's io domain APIO2_VDDPST and APIO2_VDD are 1.8V. So gpio2ab can only output 1.8V. BRANCH=none BUG=chrome-os-partner:52510 TEST=Apply this patch, CPU1_SDIO_PWREN(GPIO2_A2) can output 1.8V Change-Id: Iefe58cf5ad83a8e79916ad177d148c1036283668 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c4afee265f3f31c1defee08cb89ab3e45ff8d1a Original-Change-Id: I0216c8efb7ef9256b878adeeee0a52335bf69f93 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/337194 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
57 lines
1.8 KiB
C
57 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <soc/grf.h>
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#include <soc/spi.h>
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#include <console/console.h>
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void bootblock_mainboard_early_init(void)
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{
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/* Let gpio2ab io domains works at 1.8V.
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*
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* If io_vsel[0] == 0(default value), gpio2ab io domains is 3.0V
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* powerd by APIO2_VDD, otherwise, 1.8V supplied by APIO2_VDDPST.
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* But from the schematic of kevin rev0, the APIO2_VDD and
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* APIO2_VDDPST both are 1.8V(intentionally?).
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*
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* So, by default, CPU1_SDIO_PWREN(GPIO2_A2) can't output 3.0V
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* because the supply is 1.8V.
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* Let ask GPIO2_A2 output 1.8V to make GPIO interal logic happy.
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*/
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write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 0));
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if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
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_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
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"CONSOLE_SERIAL_UART should be UART2");
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/* iomux: select gpio4c[4:3] as uart2 dbg port */
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write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C);
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/* grf soc_con7[11:10] use for uart2 select */
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write32(&rk3399_grf->soc_con7, UART2C_SEL);
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}
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}
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void bootblock_mainboard_init(void)
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{
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/* select the pinmux for spi flashrom */
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write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
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write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
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rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
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}
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