2d4e836f11
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cache.h>
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#include <bootblock_common.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/grf.h>
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#include <soc/timer.h>
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#include <symbols.h>
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void bootblock_soc_init(void)
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{
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rkclk_init();
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mmu_init();
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/* Start with a clean slate. */
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mmu_config_range(0, 4096, DCACHE_OFF);
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/* SRAM is tightly wedged between registers, need to use subtables. Map
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* write-through as equivalent for non-cacheable without XN on A17. */
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mmu_config_range_kb((uintptr_t)_sram/KiB,
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REGION_SIZE(sram)/KiB, DCACHE_WRITETHROUGH);
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dcache_mmu_enable();
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rkclk_configure_crypto(148500*KHz);
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}
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