Kyösti Mälkki bfca67078c intel/sandybridge post-car: Redo MTRR settings and stack selection ... Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Also fixes regression of slower S3 resume path after commit 9b99152 intel/sandybridge: Use common ACPI S3 recovery Skipping low memory backup and using stage cache for ramstage decreases time spent on S3 resume path by 50 ms on samsung/lumpy. Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15790 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)		2016-11-18 21:00:30 +01:00
..
amd	northbridge/amd/agesa/family10: transition away from device_t	2016-11-15 18:19:30 +01:00
intel	intel/sandybridge post-car: Redo MTRR settings and stack selection	2016-11-18 21:00:30 +01:00
via	northbridge/via/vx800: transition away from device_t	2016-11-15 18:21:30 +01:00