c024381f8f
From doc 571118, the bit 5 of OdtConfig is nWR config. If the bit 5 is set, MRC will set MR1 nWR field to 24. If the bit 5 is clear, MRC will set MR1 nWR field to 6. Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/27814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
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acpi | ||
arch | ||
commonlib | ||
console | ||
cpu | ||
device | ||
drivers | ||
ec | ||
include | ||
lib | ||
mainboard | ||
northbridge | ||
security | ||
soc | ||
southbridge | ||
superio | ||
vendorcode | ||
Kconfig |