c02b4fc9db
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
72 lines
2 KiB
C
72 lines
2 KiB
C
#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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void setup_lapic(void)
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{
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/* this is so interrupts work. This is very limited scope --
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* linux will do better later, we hope ...
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*/
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/* this is the first way we learned to do it. It fails on real SMP
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* stuff. So we have to do things differently ...
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* see the Intel mp1.4 spec, page A-3
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*/
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#if NEED_LAPIC == 1
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/* Only Pentium Pro and later have those MSR stuff */
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msr_t msr;
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printk(BIOS_INFO, "Setting up local apic...");
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/* Enable the local apic */
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msr = rdmsr(LAPIC_BASE_MSR);
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msr.lo |= LAPIC_BASE_MSR_ENABLE;
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msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
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msr.lo |= LAPIC_DEFAULT_BASE;
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wrmsr(LAPIC_BASE_MSR, msr);
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/*
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* Set Task Priority to 'accept all'.
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*/
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lapic_write_around(LAPIC_TASKPRI,
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lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
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/* Put the local apic in virtual wire mode */
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lapic_write_around(LAPIC_SPIV,
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(lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK))
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| LAPIC_SPIV_ENABLE);
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lapic_write_around(LAPIC_LVT0,
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(lapic_read_around(LAPIC_LVT0) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK))
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| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_EXTINT)
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);
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lapic_write_around(LAPIC_LVT1,
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(lapic_read_around(LAPIC_LVT1) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK))
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| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_NMI)
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);
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printk(BIOS_DEBUG, " apic_id: 0x%02lx ", lapicid());
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#else /* !NEED_LLAPIC */
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/* Only Pentium Pro and later have those MSR stuff */
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msr_t msr;
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printk(BIOS_INFO, "Disabling local apic...");
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msr = rdmsr(LAPIC_BASE_MSR);
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msr.lo &= ~LAPIC_BASE_MSR_ENABLE;
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wrmsr(LAPIC_BASE_MSR, msr);
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#endif /* !NEED_LAPIC */
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printk(BIOS_INFO, "done.\n");
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post_code(0x9b);
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}
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