Tom Warren c05a90595d nyan*: pinmux: fix PWM1/2 conflicts ... GPIO_PU4/PH1 and _PU5/PH2 were set to use the same PWM1/2 SFIO. Even though no problems were caused by this, correct it here so we get a conflict-free pinmux map. BUG=chrome-os-partner:27091 BRANCH=none TEST=Built and booted on Nyan, ran TegraShell "pinmux check" and saw no conflicts. Original-Change-Id: Ib16341aa0c92b9a078d7f3254d4151e9592f40b0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194582 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e06a5a62d381f803dd6574787795a51ce1f1fe74) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I055359dc80c0c878ba5f5faac17884a5506a826c Reviewed-on: http://review.coreboot.org/7759 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2014-12-15 20:16:43 +01:00
..
bct	blaze: Change RAMCODE 0010 to hynix-2GB-792MHz	2014-12-15 20:12:02 +01:00
boardid.c
boardid.h
bootblock.c
chromeos.c
devicetree.cb	tegra124: set safe values for href_to_sync and vref_to_sync	2014-12-15 20:15:36 +01:00
Kconfig	nyans: prepare for vboot verification of ramstage	2014-12-15 20:14:43 +01:00
mainboard.c	spi: Factor EC protocol details out of the SPI drivers.	2014-12-09 20:32:06 +01:00
Makefile.inc
pmic.c
pmic.h
romstage.c	nyan*: pinmux: fix PWM1/2 conflicts	2014-12-15 20:16:43 +01:00
sdram_configs.c	blaze: Change RAMCODE 0010 to hynix-2GB-792MHz	2014-12-15 20:12:02 +01:00
sdram_configs.h