0949e73906
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
135 lines
3.9 KiB
C
135 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pci_type.h>
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#include <delay.h>
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void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge)
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{
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u16 reg16;
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reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
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reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
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pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
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}
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void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge)
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{
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u16 reg16;
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reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
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reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
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pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
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}
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void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary)
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{
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/* Disable config transaction forwarding. */
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pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
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pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
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/* Enable config transaction forwarding. */
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pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
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pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
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}
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static void pci_s_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size)
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{
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u16 reg16;
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/* Disable MMIO window behind the bridge. */
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reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
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pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10);
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if (!size)
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return;
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/* Enable MMIO window behind the bridge. */
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pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE,
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((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0));
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reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MEMORY;
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pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
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}
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static void pci_s_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
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{
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int timeout, ret = -1;
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/* Secondary bus number is mostly irrelevant as we disable
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* configuration transactions right after the probe.
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*/
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u8 secondary = 15;
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u8 dev = 0;
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/* Enable configuration and MMIO over bridge. */
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pci_s_assert_secondary_reset(p2p_bridge);
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pci_s_deassert_secondary_reset(p2p_bridge);
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pci_s_bridge_set_secondary(p2p_bridge, secondary);
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pci_s_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size);
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for (timeout = 20000; timeout; timeout--) {
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pci_devfn_t dbg_dev = PCI_DEV(secondary, dev, 0);
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u32 id = pci_s_read_config32(dbg_dev, PCI_VENDOR_ID);
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if (id != 0 && id != 0xffffffff && id != 0xffff0001)
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break;
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udelay(10);
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}
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if (timeout != 0)
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ret = pci_early_device_probe(secondary, dev, mmio_base);
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/* Disable MMIO window if we found no suitable device. */
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if (ret)
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pci_s_bridge_set_mmio(p2p_bridge, 0, 0);
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/* Resource allocator will reconfigure bridges and secondary bus
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* number may change. Thus early device cannot reliably use config
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* transactions from here on, so we may as well disable them.
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*/
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pci_s_bridge_set_secondary(p2p_bridge, 0);
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}
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void pci_early_bridge_init(void)
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{
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/* No PCI-to-PCI bridges are enabled yet, so the one we try to
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* configure must have its primary on bus 0.
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*/
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pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE,
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CONFIG_EARLY_PCI_BRIDGE_FUNCTION);
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pci_s_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000);
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}
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/* FIXME: A lot of issues using the following, please avoid.
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* Assumes 256 PCI buses, scans them all even when PCI bridges are still
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* disabled. Probes all functions even if 0 is not present.
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*/
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pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
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{
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for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
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unsigned int id;
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id = pci_s_read_config32(dev, 0);
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if (id == pci_id)
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return dev;
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}
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return PCI_DEV_INVALID;
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}
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pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
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{
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pci_devfn_t dev, last;
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dev = PCI_DEV(bus, 0, 0);
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last = PCI_DEV(bus, 31, 7);
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for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
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unsigned int id;
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id = pci_s_read_config32(dev, 0);
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if (id == pci_id)
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return dev;
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}
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return PCI_DEV_INVALID;
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}
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