Furquan Shaikh c0dbdf4c90 soc/intel/skylake: Fix the PCI ID for SATA controller ... Update the PCI ID for SATA controller on Kaby Lake. Change-Id: Id0b5e0366e04fbac6a57a15407f33f390a2a1856 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19395 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-04-25 18:42:29 +02:00
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acpi	src/acpi: Capitalize ACPI and SATA	2016-07-31 19:25:40 +02:00
arch	arch/x86: Add read64 and write64 functions	2017-04-25 06:14:39 +02:00
commonlib	include: Add xmalloc, xzmalloc and dma routines	2017-04-25 00:52:03 +02:00
console	console: rework log level to not be reliant on ROMSTAGE_CONST	2017-04-25 18:13:56 +02:00
cpu	AGESA: Unify heap location	2017-04-15 11:16:10 +02:00
device	device: allow devicetree accesses in postcar stage	2017-04-25 18:15:14 +02:00
drivers	lib: provide clearer devicetree semantics	2017-04-25 18:14:38 +02:00
ec	ec/roda/it8518: Do EC write manually with long timeout	2017-04-08 13:17:56 +02:00
include	lib: provide clearer devicetree semantics	2017-04-25 18:14:38 +02:00
lib	drivers/i2c/tpm: use iobuf library for marshaling commands	2017-04-24 19:07:07 +02:00
mainboard	lib: provide clearer devicetree semantics	2017-04-25 18:14:38 +02:00
northbridge	lib: provide clearer devicetree semantics	2017-04-25 18:14:38 +02:00
soc	soc/intel/skylake: Fix the PCI ID for SATA controller	2017-04-25 18:42:29 +02:00
southbridge	[nb|sb]/amd/[amdfam10|sb700]: Add LPC bridge ACPI names for NB/SB	2017-04-17 23:33:09 +02:00
superio	superio/fintek: Add support for Fintek F71808A	2017-03-27 19:19:56 +02:00
vboot	Remove libverstage as separate library and source file class	2017-03-28 22:18:53 +02:00
vendorcode	Kconfig: provide MAINBOARD_HAS_TPM_CR50 option	2017-04-24 22:02:55 +02:00
Kconfig	include: Add xmalloc, xzmalloc and dma routines	2017-04-25 00:52:03 +02:00