c1dc7932b5
XS is a read-only field of mstatus. Unable to be write. So remove this code. Change-Id: I3ad6b0029900124ac7cce062e668a0ea5a8b2c0e Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28357 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/*
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* Early initialization code for riscv virtual memory
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <arch/encoding.h>
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#include <stdint.h>
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#include <vm.h>
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/* Delegate controls which traps are delegated to the payload. If you
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* wish to temporarily disable some or all delegation you can, in a
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* debugger, set it to a different value (e.g. 0 to have all traps go
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* to M-mode). In practice, this variable has been a lifesaver. It is
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* still not quite determined which delegation might by unallowed by
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* the spec so for now we enumerate and set them all. */
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static int delegate = 0
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| (1 << CAUSE_MISALIGNED_FETCH)
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| (1 << CAUSE_FETCH_ACCESS)
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| (1 << CAUSE_ILLEGAL_INSTRUCTION)
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| (1 << CAUSE_BREAKPOINT)
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| (1 << CAUSE_LOAD_ACCESS)
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| (1 << CAUSE_STORE_ACCESS)
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| (1 << CAUSE_USER_ECALL)
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| (1 << CAUSE_FETCH_PAGE_FAULT)
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| (1 << CAUSE_LOAD_PAGE_FAULT)
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| (1 << CAUSE_STORE_PAGE_FAULT)
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;
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void mstatus_init(void)
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{
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uintptr_t ms = 0;
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ms = INSERT_FIELD(ms, MSTATUS_FS, 3);
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write_csr(mstatus, ms);
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// clear any pending timer interrupts.
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clear_csr(mip, MIP_STIP | MIP_SSIP);
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// enable machine and supervisor timer and
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// all other supervisor interrupts.
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set_csr(mie, MIP_MTIP | MIP_STIP | MIP_SSIP);
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// Delegate supervisor timer and other interrupts to supervisor mode,
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// if supervisor mode is supported.
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if (supports_extension('S')) {
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set_csr(mideleg, MIP_STIP | MIP_SSIP);
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set_csr(medeleg, delegate);
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}
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// Enable all user/supervisor-mode counters using
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// v1.10 register addresses.
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// They moved from the earlier spec.
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// Until we trust our toolchain use the hardcoded constants.
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// These were in flux and people who get the older toolchain
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// will have difficult-to-debug failures.
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write_csr(/*mcounteren*/0x306, 7);
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}
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