9ec6928b8c
Turns out the write-protect GPIO polarity for Scarlet is different than for Kevin/Gru, and nobody ever told us. Also, it must not be configured with an internal pull-up or we'll not read the correct value. This patch fixes both issues. BRANCH=scarlet BUG=b:73356326 TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the right value in all cases. Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> |
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| .. | ||
| sdram_params | ||
| board.h | ||
| board_info.txt | ||
| boardid.c | ||
| bootblock.c | ||
| chromeos.c | ||
| chromeos.fmd | ||
| devicetree.cb | ||
| devicetree.scarlet.cb | ||
| Kconfig | ||
| Kconfig.name | ||
| mainboard.c | ||
| Makefile.inc | ||
| memlayout.ld | ||
| pwm_regulator.c | ||
| pwm_regulator.h | ||
| reset.c | ||
| romstage.c | ||
| sdram_configs.c | ||