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Duncan Laurie c323036884 Update PCIe Root Port _PRT to handle re-mapped functions
The chipset enforces static-defined interrupt swizzling on PCIe root
ports so if a port is remapped to a different function it needs to
still report the proper interrupt map to the OS instead of assuming
that function number is equivalent to root port number.

This change also includes an update to the PCH function disable
register which was incorrect for CPT/PPT and would cause unpredictable
behavior if used.

The kernel command line was changed to add 'nomsi' in order to force
PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure
that the mapping is correct.

LUMPY current:

  00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
  00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)

  16:   41518   0   0   0   IO-APIC-fasteoi   i915, ahci, ath9k
  19:     720   0   0   0   IO-APIC-fasteoi   ehci_hcd:usb2, eth0

LUMPY with PCIe port coalesce enabled:

  00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
  00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)

  16:   38988   0   0   0   IO-APIC-fasteoi   i915, ahci, ath9k
  19:     347   0   0   0   IO-APIC-fasteoi   ehci_hcd:usb2, eth0

Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/978
Tested-by: build bot (Jenkins)
2012-05-01 21:21:19 +02:00
3rdparty@1925339dfb Add 3rdparty as submodule 2012-05-01 00:08:37 +02:00
documentation Whitespace/typo/cosmetic fixes (trivial). 2010-09-23 18:48:27 +00:00
payloads Update SeaBIOS stable to the version 1.7.0 tag. 2012-04-29 22:51:08 +02:00
src Update PCIe Root Port _PRT to handle re-mapped functions 2012-05-01 21:21:19 +02:00
util abuild: Add option to use binary files 2012-05-01 00:28:01 +02:00
.gitignore romcc: kill gcc warnings and .gitignore generated files 2012-02-07 22:34:42 +01:00
.gitmodules Add 3rdparty as submodule 2012-05-01 00:08:37 +02:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile Keep cscope.out when distclean. 2012-03-31 12:06:10 +02:00
Makefile.inc Add vsa processor to cbfs-files 2012-05-01 11:35:28 +02:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.